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VLSI Design
Volume 10 (1999), Issue 1, Pages 1-20
http://dx.doi.org/10.1155/1999/81698

Accurate Interconnection Length Estimations for Predictions Early in the Design Cycle

University of Ghent, Department of Electronics and Information Systems, St.-Pietersnieuwstraat 41, Gent B-9000, Belgium

Received 7 September 1998; Accepted 20 November 1998

Copyright © 1999 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [22 citations]

The following is the list of published articles that have cited the current article.

  • P. Christie, and D. Stroobandt, “The interpretation and application of Rent's rule,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 6, pp. 639–648, 2000. View at Publisher · View at Google Scholar
  • A.B. Kahng, S. Mantik, and D. Stroobandt, “Toward accurate models of achievable routing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 5, pp. 648–659, 2001. View at Publisher · View at Google Scholar
  • P. Christie, “A differential equation for placement analysis,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 6, pp. 913–921, 2001. View at Publisher · View at Google Scholar
  • D Stroobandt, Ck Cheng, B Liu, and Ab Kahng, “Toward better wireload models in the presence of obstacles,” Ieee Transactions On Very Large Scale Integration (Vlsi) Systems, vol. 10, no. 2, pp. 177–189, 2002. View at Publisher · View at Google Scholar
  • P. Gopalakrishnan, A. Odabasioglu, L. Pileggi, and S. Raje, “An analysis of the wire-load model uncertainty problem,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 1, pp. 23–31, 2002. View at Publisher · View at Google Scholar
  • Xiaojian Yang, R. Kastner, and M. Sarrafzadeh, “Congestion estimation during top-down placement,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 1, pp. 72–80, 2002. View at Publisher · View at Google Scholar
  • Yu Cao, Chenming Hu, Xuejue Huang, A.B. Kahng, I.L. Markov, M. Oliver, D. Stroobandt, and D. Sylvester, “Improved a priori interconnect predictions and technology extrapolation in the GTX system,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 1, pp. 3–14, 2003. View at Publisher · View at Google Scholar
  • Dirk Stroobandt, “A priori wire length distribution models with multiterminal nets,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 1, pp. 35–43, 2003. View at Publisher · View at Google Scholar
  • Suhrid A. Wadekar, and Alice C. Parker, “Interconnect-based system-level energy and power prediction to guide architecture exploration,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 4, pp. 373–380, 2004. View at Publisher · View at Google Scholar
  • Haldun M. Ozaktas, “Information flow and interconnections in computing: extensions and applications of Rent's rule,” Journal of Parallel and Distributed Computing, vol. 64, no. 12, pp. 1360–1370, 2004. View at Publisher · View at Google Scholar
  • Chao-Yang Yeh, and Malgorzata Marek-Sadowska, “Sequential delay budgeting with interconnect prediction,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 10, pp. 1028–1037, 2004. View at Publisher · View at Google Scholar
  • Qinghua Liu, Bo Hu, and M. Marek-Sadowska, “Individual wire-length prediction with application to timing-driven placement,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 10, pp. 1004–1014, 2004. View at Publisher · View at Google Scholar
  • Hongyu Chen, Chung-Kuan Cheng, A.B. Kahng, I.I. Mandoiu, Qinke Wang, and Bo Yao, “The Y architecture for on-chip interconnect: analysis and methodology,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 4, pp. 588–599, 2005. View at Publisher · View at Google Scholar
  • Qinghua Liu, and M. Marek-Sadowska, “Semi-individual wire-length prediction with application to logic synthesis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 4, pp. 611–624, 2006. View at Publisher · View at Google Scholar
  • Shweta Shah, Nazanin Mansouri, and Adrian Nunez-Aldana, “Pre-layout estimation of interconnect lengths for digital integrated circuits,” Proceedings of the 16th IEEE International Conference on Electronics, Communications and Computers, CONIELECOMP 2006, vol. 2006, pp. 38, 2006. View at Publisher · View at Google Scholar
  • Taraneh Taghavi, Ani Nahapetian, and Majid Sarrafzadeh, “System level estimation of interconnect length in the presence of IP blocks,” Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007, pp. 438–443, 2007. View at Publisher · View at Google Scholar
  • Shuhei Amakawa, Takumi Uezono, Takashi Sato, Kenichi Okada, and Kazuya Masu, “Adaptable wire-length distribution with tunable occupation probability,” International Workshop on System Level Interconnect Prediction, SLIP, pp. 1–8, 2007. View at Publisher · View at Google Scholar
  • Taraneh Taghavi, Foad Dabiri, Ani Nahapetian, and Majid Sarrafzadeh, “Tutorial on congestion prediction,” International Workshop on System Level Interconnect Prediction, SLIP, pp. 15–24, 2007. View at Publisher · View at Google Scholar
  • Srinivas Katkoori, and Vyas Krishnan, “Clock period minimization with iterative binding based on stochastic wirelength estimation during high-level synthesis,” Proceedings of the IEEE International Frequency Control Symposium and Exposition, pp. 641–646, 2008. View at Publisher · View at Google Scholar
  • Madhu S. Sibi Govindan, Stephen W. Keckler, and Doug Burger, “End-to-end validation of architectural power models,” Proceedings of the International Symposium on Low Power Electronics and Design, pp. 383–388, 2009. View at Publisher · View at Google Scholar
  • Deming Chen, Jason Cong, Yiping Fan, and Lu Wan, “LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 4, pp. 564–577, 2010. View at Publisher · View at Google Scholar
  • Dirk Stroobandt, “Interconnect research influenced,” IEEE Solid-State Circuits Magazine, vol. 2, no. 1, pp. 21–27, 2010. View at Publisher · View at Google Scholar