Table of Contents
VLSI Design
Volume 10, Issue 1, Pages 35-55
http://dx.doi.org/10.1155/1999/85272

Logic Synthesis for a Regular Layout

1Electrical and Computer Engineering Department, Portland State University, 1800 6th Avenue, Portland 97207-0751, OR, USA
2Lattice Semiconductor Corporation, 5555 NE Moore Count, Hillsboro 97124-0118, OR, USA

Received 7 September 1998; Accepted 20 November 1998

Copyright © 1999 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Malgorzata Chrzanowska-Jeske, Yang Xu, and Marek Perkowski, “Logic Synthesis for a Regular Layout,” VLSI Design, vol. 10, no. 1, pp. 35-55, 1999. https://doi.org/10.1155/1999/85272.