Table of Contents
VLSI Design
Volume 11, Issue 2, Pages 137-147

An Efficient Parallel VLSI Sorting Architecture

1Research Group, Sabre, Inc., 1 East Kirkwood Blvd., MD 7390, Southlake 76092, TX, USA
2Department of Computer Science, Box 830688, MS EC31, University of Texas at Dallas, Richardson 75083-0688, TX, USA

Received 10 January 1999; Accepted 6 December 1999

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


We present a new parallel sorting algorithm that uses a fixed-size sorter iteratively to sort inputs of arbitrary size. A parallel sorting architecture based on this algorithm is proposed. This architecture consists of three components, linear arrays that support constant-time operations, a multilevel sorting network, and a termination detection tree, all operating concurrently in systolic processing fashion. The structure of this sorting architecture is simple and regular, highly suitable for VLSI realization. Theoretical analysis and experimental data indicate that the performance of this architecture is likely to be excellent in practice.