Table of Contents
VLSI Design
Volume 11, Issue 2, Pages 137-147

An Efficient Parallel VLSI Sorting Architecture

1Research Group, Sabre, Inc., 1 East Kirkwood Blvd., MD 7390, Southlake 76092, TX, USA
2Department of Computer Science, Box 830688, MS EC31, University of Texas at Dallas, Richardson 75083-0688, TX, USA

Received 10 January 1999; Accepted 6 December 1999

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Yanjun Zhang and S. Q. Zheng, “An Efficient Parallel VLSI Sorting Architecture,” VLSI Design, vol. 11, no. 2, pp. 137-147, 2000.