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VLSI Design
Volume 11, Issue 2, Pages 161-173
http://dx.doi.org/10.1155/2000/18189

Delay Time Estimation Model for Large Digital CMOS Circuits

1Dept. Electronic Materials Engineering, Kwangwoon University, 447-1 Wolgye-Dong Nowon-Gu, Seoul 139-701, Korea
2System MCU Team, Samsung Electronics Co. Ltd., San 24 Nongseo-Lee Gihung-Eup, Yongin-Si Kyounggi-Do, 449-711, Korea

Received 2 February 1999; Accepted 15 August 1999

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Delay time estimation in simulation or design verification step during a design cycle has become more and more important as the meaning of performance prediction. This paper proposed a delay estimation model for digital CMOS circuits, which works in gate-level but the modeling process includes the characteristics of MOSFETs. This model can handle the variation according to the kind of gates, input transition time, output load(fan-out), and transistor sizes of a gate. The procedure to find the general model was that, a delay model for CMOS inverter was extracted first, then it was extended to other gate by converting it into an equivalent inverter. The resulting model was evaluated and compared with SPICE simulation, which showed that the proposed model has the accuracy of less than 5% relative error rate to the SPICE results for each case and the speed of about 70 times faster than SPICE.