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VLSI Design
Volume 11 (2000), Issue 2, Pages 161-173

Delay Time Estimation Model for Large Digital CMOS Circuits

1Dept. Electronic Materials Engineering, Kwangwoon University, 447-1 Wolgye-Dong Nowon-Gu, Seoul 139-701, Korea
2System MCU Team, Samsung Electronics Co. Ltd., San 24 Nongseo-Lee Gihung-Eup, Yongin-Si Kyounggi-Do, 449-711, Korea

Received 2 February 1999; Accepted 15 August 1999

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Dong-Wook Kim and Tae-Yong Choi, “Delay Time Estimation Model for Large Digital CMOS Circuits,” VLSI Design, vol. 11, no. 2, pp. 161-173, 2000. doi:10.1155/2000/18189