Table of Contents
VLSI Design
Volume 11, Issue 4, Pages 397-403

Low Power VLSI Implementation of the DCT on Single Multiplier DSP Processors

Electronics and Electrical Eng. Department, University of Edinburgh, Kings Buildings Edinburgh, EH9 3JL, UK

Received 5 June 1999; Accepted 2 September 1999

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [1 citation]

The following is the list of published articles that have cited the current article.

  • Majdi Elhaji, Abdlekrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, and Rached Tourki, “A low power and highly parallel implementation of the H.264 8 × 8 transform and quantization,” 2010 IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2010, pp. 528–531, 2011. View at Publisher · View at Google Scholar