Table of Contents
VLSI Design
Volume 11, Issue 2, Pages 107-113
http://dx.doi.org/10.1155/2000/52658

A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop

Dept. of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan

Received 5 June 1999; Accepted 1 October 1999

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Chua-Chin Wang, Yu-Tsun Chien, and Ying-Pei Chen, “A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop,” VLSI Design, vol. 11, no. 2, pp. 107-113, 2000. https://doi.org/10.1155/2000/52658.