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VLSI Design
Volume 11 (2000), Issue 2, Pages 129-136

νMOS-based Sorter for Arithmetic Applications

1Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica, Edif. CICA, Avda. Reina Mercedes s/n, Sevilla 41012, Spain
2Instituto de Microelectrónica de Sevilla, IMSE-CNM, Universidad de Sevilla. Edif. CICA, Avda. Reina Mercedes s/n, Sevilla 41012, Spain

Received 1 June 1999; Accepted 22 November 1999

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing some arithmetic demonstrators. In particular, both an (8 × 8)-multiplier and a (15, 4) counter which use a sorter as the main building block have been implemented. Traditional disadvantages of binary sorters such as their hardware intensive nature are avoided by using νMOS circuits. It allows both an improving of previous results for multipliers based on a similar architecture, and to obtain a new type of counter which shows a reduced delay when compared to a conventional implementation.