Table of Contents
VLSI Design
Volume 11, Issue 2, Pages 129-136
http://dx.doi.org/10.1155/2000/57240

νMOS-based Sorter for Arithmetic Applications

1Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica, Edif. CICA, Avda. Reina Mercedes s/n, Sevilla 41012, Spain
2Instituto de Microelectrónica de Sevilla, IMSE-CNM, Universidad de Sevilla. Edif. CICA, Avda. Reina Mercedes s/n, Sevilla 41012, Spain

Received 1 June 1999; Accepted 22 November 1999

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [3 citations]

The following is the list of published articles that have cited the current article.

  • P. Celinski, D. Abbott, and S.D. Cotofana, “Area efficient, high speed parallel counter circuits using charge recycling threshold logic,” Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03., vol. 5, pp. V-233–V-236, . View at Publisher · View at Google Scholar
  • Peter Celinski, Sorin D. Cotofana, and Derek Abbott, “Threshold logic parallel counters for 32-bit multipliers,” Proceedings of SPIE - The International Society for Optical Engineering, vol. 4935, pp. 205–214, 2002. View at Publisher · View at Google Scholar
  • Peter Celinski, Sorin D. Cotofana, José F. López, Said Al-Sarawi, and Derek Abbott, “State-of-the-art in CMOS threshold-logic VLSI gate implementations and applications,” Proceedings of SPIE - The International Society for Optical Engineering, vol. 5117, pp. 53–64, 2003. View at Publisher · View at Google Scholar