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VLSI Design
Volume 10, Issue 3, Pages 249-263
http://dx.doi.org/10.1155/2000/71046

An Edge-endpoint-based Configurable Hardware Architecture for VLSI Layout Design Rule Checking

1Department of Electrical Engineering, Princeton University, Princeton 08544, NJ, USA
2NEC CCRL, Princeton 08540, NJ, USA

Received 1 February 1999; Accepted 1 October 1999

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Zhen Luo, Margaret Martonosi, and Pranav Ashar, “An Edge-endpoint-based Configurable Hardware Architecture for VLSI Layout Design Rule Checking,” VLSI Design, vol. 10, no. 3, pp. 249-263, 2000. https://doi.org/10.1155/2000/71046.