VLSI Design

VLSI Design / 2000 / Article

Open Access

Volume 11 |Article ID 076384 | https://doi.org/10.1155/2000/76384

Chaeryung Park, Taewhan Kim, C. L. Liu, "An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization", VLSI Design, vol. 11, Article ID 076384, 16 pages, 2000. https://doi.org/10.1155/2000/76384

An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization

Received05 Jun 1999
Accepted21 Dec 1999

Abstract

This paper presents an integrated approach to data path synthesis which solves three important design problems: scheduling, allocation, and hardware partitioning with power minimization as a key design objective. Based on the rules of thumbs introduced in prior work on synthesis for low power we derive an integer programming formulation for solving the problems. We then, based on the formulation, develop an efficient algorithm which performs scheduling, allocation and hardware partitioning simultaneously so that the effects of them on power consumption are exploited more fully and effectively. Our experimentation results show that the algorithm is quite effective, producing designs with significant savings in power consumption.

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


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