Table of Contents Author Guidelines Submit a Manuscript
VLSI Design
Volume 11, Issue 4, Pages 405-415
http://dx.doi.org/10.1155/2000/81057

A Chip for a Routing Table Based on a Novel Modified Trie Algorithm

CINVESTAV del IPN, Research and Advanced Studies Center of National Politechnic Institute, Apartado Postal 31-438, Guadalajara C.P. 44550, Jalisco, Mexico

Received 5 June 1999; Accepted 10 February 2000

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

D. Torres, A. Larios, and M. Guzmán, “A Chip for a Routing Table Based on a Novel Modified Trie Algorithm,” VLSI Design, vol. 11, no. 4, pp. 405-415, 2000. https://doi.org/10.1155/2000/81057.