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VLSI Design
Volume 12 (2001), Issue 1, Pages 69-79

A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model

1VLSI Design Lab., Dept. of Electrical and Computer Eng., University of Patras, 26110, Greece
2VLSI Design and Testing Center, Dept. of Electrical and Computer Eng., Democritus University of Thrace, Xanthi 67100, Greece

Received 24 September 1999; Revised 6 October 1999

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Our aim is the development of a novel probabilistic method to estimate the power consumption of a combinational circuit under real gate delay model handling temporal, structural and input pattern dependencies. The chosen gate delay model allows handling both the functional and spurious transitions. It is proved that the switching activity evaluation problem assuming real gate delay model is reduced to the zero delay switching activity evaluation problem at specific time instances. A modified Boolean function, which describes the logic behavior of a signal at any time instance, including time parameter is introduced. Moreover, a mathematical model based on Markov stochastic processes, which describes the temporal and spatial correlation in terms of the associated zero delay based parameters is presented. Based on the mathematical model and considering the modified Boolean function, a new algorithm to evaluate the switching activity at specific time instances using Ordering Binary Decision Diagrams (OBBDs) is also presented. Comparative study of benchmark circuits demonstrates the accuracy and efficiency of the proposed method.