Table of Contents Author Guidelines Submit a Manuscript
VLSI Design
Volume 12, Issue 2, Pages 125-138
http://dx.doi.org/10.1155/2001/65638

Power Optimization of Delay Constrained Circuits

1#L458, Technological Institute, 2145 Sheridan Road, Evanston, IL 60208, USA
2#L463, Technological Institute, 2145 Sheridan Road, Evanston, IL 60208, USA
3#L469, Technological Institute, 2145 Sheridan Road, Evanston, IL 60208, USA

Received 20 June 2000; Revised 3 August 2000

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Anshuman Nayak, Malay Haldar, Prith Banerjee, Chunhong Chen, and Majid Sarrafzadeh, “Power Optimization of Delay Constrained Circuits,” VLSI Design, vol. 12, no. 2, pp. 125-138, 2001. https://doi.org/10.1155/2001/65638.