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VLSI Design
Volume 12 (2001), Issue 2, Pages 245-273

An Instruction-Level Power Analysis Model with Data Dependency

1Dipartimento di Ingegneria Informatica e delle Telecomunicazioni, Università di Catania, V.le. A. Doria, Catania 6–95125, Italy
2STMicroelectronics, Stradale Primosole, Catania 95100, Italy

Received 20 June 2000; Revised 3 August 2000

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Power constraints are becoming a critical design issue in the field of portable microprocessor systems. The impact of software on overall system power is becoming increasingly important as more and more digital applications are implemented as embedded systems, part of which are hardware (ASICs) and part software in which a specific application is executed on a processor. In this paper, a data-dependent instruction-level power analysis model is presented. It is compared with the average cost model proposed by Tiwari et al. [1] in both estimation accuracy and characterisation time. The data-dependent model can be generalised to be applied to generic RISC processor. Application of the data-dependent model we propose sensibly reduces errors in estimating software power consumption per clock cycle which is lower than 10%, in the case of the ST20-C2P core.