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VLSI Design
Volume 12, Issue 1, Pages 53-60
http://dx.doi.org/10.1155/2001/96353

A Fast Algorithm for Transistor Folding

Department of Computer and Information Science and Engineering, University of Florida, Gainesville 32611-6120, FL, USA

Received 13 July 1999; Revised 20 September 1999

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Transistor folding reduces the area of row-based designs that employ transistors of different size. Kim and Kang [1] have developed an O(m2 log m) algorithm to optimally fold m transistor pairs. In this paper we develop an O(m2) algorithm for optimal transistor folding. Our experiments indicate that our algorithm runs 3 to 60 times as fast for m values in the range (100, 100,000).