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VLSI Design
Volume 12, Issue 1, Pages 53-60
http://dx.doi.org/10.1155/2001/96353

A Fast Algorithm for Transistor Folding

Department of Computer and Information Science and Engineering, University of Florida, Gainesville 32611-6120, FL, USA

Received 13 July 1999; Revised 20 September 1999

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [6 citations]

The following is the list of published articles that have cited the current article.

  • Gustavo H. Smaniotto, Joao J. S. Machado, Matheus T. Moreira, Adriel M. Ziesemer, Felipe S. Marques, and Leomar S. da Rosa, “Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool,” 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS), pp. 355–358, . View at Publisher · View at Google Scholar
  • Gustavo H. Smaniotto, Matheus T. Moreira, Adriel M. Ziesemer, Felipe S. Marques, and Leomar S. da Rosa, “Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding,” 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1–4, . View at Publisher · View at Google Scholar
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  • Xun Chen, Jianwen Zhu, and Minxuan Zhang, “Regular FPGA based on regular fabric,” Journal of Semiconductors, vol. 32, no. 8, pp. 085015, 2011. View at Publisher · View at Google Scholar
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