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VLSI Design
Volume 12, Issue 1, Pages 53-60
http://dx.doi.org/10.1155/2001/96353

A Fast Algorithm for Transistor Folding

Department of Computer and Information Science and Engineering, University of Florida, Gainesville 32611-6120, FL, USA

Received 13 July 1999; Revised 20 September 1999

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Edward Y. C. Cheng and Sartaj Sahni, “A Fast Algorithm for Transistor Folding,” VLSI Design, vol. 12, no. 1, pp. 53-60, 2001. https://doi.org/10.1155/2001/96353.