Research Article  Open Access
Sotoudeh HamediHagh, Ahmet Bindal, "Design and Characterization of the Next Generation Nanowire Amplifiers", VLSI Design, vol. 2008, Article ID 190315, 5 pages, 2008. https://doi.org/10.1155/2008/190315
Design and Characterization of the Next Generation Nanowire Amplifiers
Abstract
Vertical nanowire surrounding gate field effect transistors (SGFETs) provide full gate control over the channel to eliminate shortchannel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10?nm channel length and a 2?nm channel radius. The amplifier dissipates 5?W power and provides 5?THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5?V, and a distortion better than 3% from a 1.8?V power supply and a 20?aF capacitive load. The 2nd and 3rdorder harmonic distortions of the amplifier are 40?dBm and 52?dBm, respectively, and the 3rdorder intermodulation is 24?dBm for a twotone input signal with 10?mV amplitude and 10?GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation highspeed analog and VLSI technologies.
1. Introduction
The speed of silicon integrated circuits is reaching beyond 100?GHz to enable wireless communications with wideband channels [1]. Even though the current VLSI technology has approached to its scaling limits necessitating a replacement technology, siliconbased devices are still favored to realize largescale circuits and systems because of their low cost.
Downscaling of the bulk metal oxide semiconductor field effect transistors (MOSFETs) to nanometer dimensions has increased the leakage current and shortchannel effects. Therefore, alternative silicon compatible transistor devices such as silicon on insulator (SOI) MOSFETs, FinFETs, and nanotube FETs have been investigated for improved performance [2].
Vertical surrounding gate field effect transistors (SGFETs) have full gate control around channel and have minimized shortchannel effects [3]. The elimination of bulk in these transistors reduces latchup and substrate noise. The layout views of a vertical nanowire SGFET and a planar bulk MOSFET are shown in Figure 1 for comparison. Both transistors have identical channel widths of 13?nm and channel lengths of 10?nm and are designed with similar layout design rules. The area of the vertical transistor is (40?nm 40?nm) 1600?n, and the area of the planar transistor is also 1600?n (76?nm 21?nm) with body contact.
(a)
(b)
2. HighFrequency Modeling
The threedimensional view and the corresponding parasitic components of the vertical nanowire SGFET are shown in Figure 2. Only, the dominant parasitics are considered to simplify the circuit model.
The intrinsic transistor is modeled using a BSIMSOI compatible model to ensure that all the input and output transfer characteristics of the circuit and device simulators match each other. The parasitic capacitance between the source contacts and the metal gate is denoted as in the figure. The parasitic capacitance, , between the metal gate and the concentric source makes contact, and the junction well is the largest dominant capacitor of the SGFET device. The gate and drain capacitors ( and ) and the drain and source capacitors ( and ) can be lumped into and , respectively. Compared to planar bulk transistors, is very small and there is no junction to bulk capacitance, therefore, is quite linear. The well resistance, , can be quite large and is the major drawback of the vertical SGFETs compared with planar transistors. The magnitude of this resistance can be reduced drastically by placing a concentric (ring shape) source contact in parallel with the well, as shown in the figure.
The simplified parasitic components associated with NMOS and PMOS SGFETs are shown in Figures 3(a) and 3(b). For accurate circuit level simulations, the intrinsic SGFETs ( and ) are modeled using BSIMSOI.
(a)
(b)
For simplified hand calculations and finding the AC parameters of the amplifiers, designed using SGFETs, the linearized smallsignal model shown in Figure 4 can be used. Using this model at low frequencies, the DC voltage gain and output resistance of various amplifier stages can be calculated. The model shown in Figure 4 is valid for transistors biased in the active operating region, and transistor models in triode or cutoff regions can be easily constructed from this model by minor modifications.
3. DifferentialPair Amplifier
The full gate control and the low leakage current of SGFETs make them suitable for many digital applications [4]. Operational amplifiers are one of the most important building blocks of analog integrated circuits, and differentialpair amplifiers are the input building blocks of any opamp, as shown in Figure 5. Therefore, the performance of a differentialpair amplifier, designed using SGFETs, needs to be measured before designing an opamp and will be investigated in this work. We design the input transistors of the differential pair amplifier using PMOS transistors to enable realizing the Miller stage using NMOS transistors and achieving higher gains.
The lowfrequency small signal model of the differential pair amplifier designed using SGFETs is shown in Figure 6.
The layout of the differential pair amplifier realized using 3 metallization layers is presented in Figure 7. All interconnect parasitics are extracted and added to the amplifier netlist for postlayout simulations.
The resistor is given by The voltage gain of the differential pair amplifier is given by where denotes and denotes .
For , the voltage gain is approximately given by
For , the output resistance is approximately given by
The main transistors of the input differential pair amplifier are realized by parallel combination of two ptype SGFETs to ensure a large transconductance. The width of the metal interconnects is selected to be 14?nm to reduce their resistivity, and four parallel vias are used to connect metal2 and metal3 layers to minimize the signal loss. Each via with 4?nm 4?nm dimension and 36?nm height has a resistance of 400?. Overlap capacitance between metal1 and metal2 routing interconnects is 0.2?aF for 14?nm 14?nm dimension and 36?nm height. The layout area of the differential pair amplifier is ?nm and ?nm.
4. Postlayout Characteristics
The transient and frequency responses of the SGFET differential pair amplifier are shown in Figure 8. The amplifier provides a gain of 16 with the first pole located at 100?GHz and the second pole located at 100?THz. To attain high accuracy in the transfer functions of various analog circuits such as switch capacitor filters and amplifiers, it might be necessary to cascade multiple stages in nested Miller architectures and achieve a voltage gain higher than 1000.
(a)
(b)
(c)
(d)
The spectrum of the output waveform of the amplifier is given in Figure 9. It has very good linearity characteristics, and the total harmonic distortions of the amplifier are only 3% for ±233?mV output swing. Such a high linearity is due to the source resistance, , acting as the degeneration resistance and minimizing the harmonic distortions of input differential pair transistors.
The postlayout characteristics of the opamp are listed in Table 1. The good performance of the SGFET amplifier indicates that these transistors are good choices for future integration of highspeed and lowpower analog and mixed signal circuits.

5. Conclusions
The design and characteristics of a differential pair amplifier designed using nanowire SGFETs and having channel length of 10?nm and channel radius of 2?nm were presented. The amplifier dissipates 5?W power and provides 5?THz bandwidth with a voltage gain of 16 and a distortion better than 3%. All these parameters indicate that vertical nanowire SGFETs are promising candidates for realizing next generation highspeed analog integrated circuits.
References
 B. Heydari, M. Bohsali, E. Adabi, and A. M. Niknejad, “Millimeterwave devices and circuit blocks up to 104 GHz in 90 nm CMOS,” IEEE Journal of SolidState Circuits, vol. 42, no. 12, pp. 2893–2903, 2007. View at: Publisher Site  Google Scholar
 A. Bindal, A. Naresh, P. Yuan, K. K. Nguyen, and S. HamediHagh, “The design of dual work function CMOS transistors and circuits using silicon nanowire technology,” IEEE Transactions on Nanotechnology, vol. 6, no. 3, pp. 291–302, 2007. View at: Publisher Site  Google Scholar
 K. H. Cho, K. H. Yeo, Y. Y. Yeoh et al., “Experimental evidence of ballistic transport in cylindrical gateallaround twin silicon nanowire metaloxidesemiconductor fieldeffect transistors,” Applied Physics Letters, vol. 92, no. 5, Article ID 052102, 3 pages, 2008. View at: Publisher Site  Google Scholar
 A. Bindal and S. HamediHagh, “An exploratory design study of a $16\times 16$ static random access memory using silicon nanowire transistors,” Journal of Nanoelectronics and Optoelectronics, vol. 2, no. 3, pp. 294–303, 2007. View at: Publisher Site  Google Scholar
Copyright
Copyright © 2008 Sotoudeh HamediHagh and Ahmet Bindal. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.