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VLSI Design
Volume 2008, Article ID 596146, 9 pages
http://dx.doi.org/10.1155/2008/596146
Research Article

Choice of a High-Level Fault Model for the Optimization of Validation Test Set Reused for Manufacturing Test

1Grenoble Institute of Technology (LCIS), 50 Rue B. de Laffemas, BP54, 26092 Valence Cedex 9, France
2STMicroelectronics, 850 Rue Jean Monnet, 38926 Crolles Cedex, France

Received 11 October 2007; Accepted 9 April 2008

Academic Editor: Bozena Kaminska

Copyright © 2008 Yves Joannon et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Yves Joannon, Vincent Beroulle, Chantal Robach, Smail Tedjini, and Jean-Louis Carbonero, “Choice of a High-Level Fault Model for the Optimization of Validation Test Set Reused for Manufacturing Test,” VLSI Design, vol. 2008, Article ID 596146, 9 pages, 2008. https://doi.org/10.1155/2008/596146.