VLSI Design

VLSI Design / 2008 / Article

Research Article | Open Access

Volume 2008 |Article ID 912536 | https://doi.org/10.1155/2008/912536

Ahmet Tekin, Mehmet R. Yuce, Wentai Liu, "Integrated VCOs for Medical Implant Transceivers", VLSI Design, vol. 2008, Article ID 912536, 10 pages, 2008. https://doi.org/10.1155/2008/912536

Integrated VCOs for Medical Implant Transceivers

Academic Editor: Yong-Bin Kim
Received02 Apr 2008
Accepted08 May 2008
Published11 Jun 2008

Abstract

The 402–405 MHz medical implant communication service (MICS) band has recently been allocated by the US Federal Communication Commission (FCC) with the potential to replace the low-frequency inductive coupling techniques in implantable devices. This band was particularly chosen to provide full-integration, low-power, faster data transfer, and longer communication range. This paper investigates the design of a voltage-controlled oscillator (VCO) that will be an essential building block of such wireless implantable devices operating in the MICS service band. Three different integrated quadrature VCOs that meet the requirements of the MICS standard are designed in 0.18 m TSMC CMOS process to propose an optimum choice. Their performances in terms of power consumption, die area, linearity, and phase noise are compared. The fabricated VCOs are a four-stage differential ring VCO, an LC tank VCO directly loaded with a poly-phase filter, and an 800 MHz LC tank VCO with a high-frequency master-slave divider. All three architectures target a VCO gain of Kvco = 15 MHz/V with 3 calibration control and 2 frequency-shift keying (FSK) control signals and are designed for 1.5 V supply voltage in a 0.18-m standard CMOS process.

1. Introduction

Design of implantable miniature devices to be able to record or to transmit real-time physiologic parameters (e.g., ECG, EEG, EOG, EMG, Neural, Blood Flow, Blood Pressure, etc.) from a patient body in medical environments is becoming very important research area. FCC has recently allocated a new band at 402–405 MHz with 300 kHz channels to enable the wireless communication of such implantable devices to deliver high level of comfort, mobility, and better patient care [1]. In addition to medical implants, metrological aids service has primary allocation at 402–405 MHz band and the Earth exploration-satellite service together with metrological-satellite service has secondary allocation at 402-403 MHz [2]. With the advance of radio frequency IC (RFIC) technology, this frequency band promises high-level integration (compared to inductive link designs) which results in miniaturization and low-power consumption. In addition, there exist relatively insignificant penetration loss at these frequencies (10 dB with 10 mm tissue penetration) [3] and is therefore very suitable for the above applications. Although higher frequency causes higher penetration loss, high-level integration becomes difficult at low frequencies. Moreover, a small antenna design is also difficult at lower frequencies [4]. Combining all these with the availability of the 402-403 MHZ band internationally, this frequency band offers an attractive choice for future medical implant devices [5].

Low power consumption and full integration are the most critical targets for implantable transceivers. Recently, some low-power CMOS transceivers, working at 433 MHz and 435 MHz bands, have been reported [68]. These designs achieve low-power operation, leaving the matching networks or voltage-controlled oscillator (VCO) tank inductor off-chip. As the size of an implantable transceiver is required to be low, the VCOs presented in this paper are designed as fully integrated. A direct conversion frequency-shift-keyed (FSK) transceiver shown in Figure 1 is selected for a low-power implantation because of the simple demodulation process of FSK signals when used with an direct conversion architecture [5, 9]. The system in Figure 1 is based on a half full-duplex communication system, namely, it does not receive and transmit at the same time. In the receive mode, the VCO is in the PLL loop. In the transmit mode of the architecture, the PLL loop opens and the base-band digital data directly modulate the VCO with an offset tone of  kHz fitting optimally into one of ten 300 kHz channels. The technique can easily be used for other modulation schemes as well (e.g., AM/FM/PM, etc.). Herein, we are mainly interested in the direct modulation of VCOs for FSK signals because of the relaxed bandwidth requirements per channel (20 kb/s maximum data rate). When the input to the VCOs is analog data, then an FM modulated signal will be generated [10]. The detailed specifications of the proposed architecture were discussed in [11].

The rest of the paper is organized as follows. Section 2 discusses the details of the phase-locked loop (PLL) architecture for an MICS transceiver. In Section 3, the design including a 402 MHz VCO directly loaded with a single-stage poly phase filter is presented. In Section 4, the performance of an 800 MHz VCO followed by a high frequency master-slave divider is discussed. Section 5 presents a four-stage differential ring VCO as a very low-power candidate for the implantable devices in the MICS band. Section 6 is the conclusion that does a performance comparison of the three different architectures targeting the same specifications with a minimal power.

2. Pll Architecture

The block diagram of the target PLL architecture for this application is shown in Figure 2(a). A choice of fractional-N PLL with 128/129 division ratio is considered with a reference oscillator of ~3.14 MHz. With this selection, the whole 3-MHz MICS band (420–405 MHz) is covered. All of the VCOs designed here employ direct modulation, where the base-band data arrange the frequency tones of FSK signals in the transmit mode. To utilize a precise reference frequency, crystal oscillators are generally used, but they increase the package size. We are investigating alternate methods such as using an on-chip temperature compensated relaxation oscillator. The main reason for choosing the proposed architecture in Figure 2(a) is to have an on-chip temperature compensated relaxation oscillator to generate the frequency reference instead of a bulky off-chip crystal. Some designs reported in the literature have successfully demonstrated sub-100 ppm accuracy across temperature and supply variations [12, 13]. Such an integrated device would inevitably contribute substantial phase noise. Direct open loop modulation of the VCO in the transmit mode and very low loop bandwidth PLL can alleviate this problem.

In order to minimize the center frequency variations in the transmit mode, the VCO gain is kept very low. This reduces the susceptibility of the oscillation frequency to the noise on the control voltage. However, having a narrow tuning range might leave the VCO frequency range out of the desired band, considering the effect of process variations. To prevent this to happen, a second static calibration loop is utilized to maintain the VCO frequency in the desired range. Two comparators track the control voltage and step the VCO frequency up or down with three-bit resolution, in case the control voltage exceeds the predefined limits. Total of 8 overlapping frequency clusters provides large enough overall tuning range while still keeping the VCO gain very low in every cluster. Overlapping regions between the clusters should be kept large enough to prevent unstable switching among the clusters due to noise and temperature variations. Moreover, by setting the thresholds of these comparators properly, the VCO is easily kept in the linear regions of its total tuning range.

Unlike the other mobile communication circuits, the phase noise requirement of a VCO for the targeted application (i.e., MICS regulation) is not stringent due to the low regulated power and short communication distance [5]. Because of the fixed distance and upper bound on EIRP (equivalent isotropically radiated power), the dynamic range is not too high (set by the path loss in 2 m, ~30 dB [11]). For this reason, the down conversion of the noise in the adjacent channel due to the phase noise of the oscillator is not very detrimental (except strong outside interferers). Assuming a signal-to-noise ratio (SNR) of 10 dB due to the next channel, the phase noise requirement of the VCO can be driven with the help of Figure 2(b) as [14] where the transmission data rate is selected 20 kb/s to cover the majority of physiological signals [3, 8, 11]. All of the different VCOs presented in the following sections were designed for the same specifications described so far, targeting the minimum power consumption with 3-bit calibration control (~15 MHz/V VCO gain in every cluster) and 2-bit FSK control ( kHz to 80 kHz). They are followed by the same two-stage single-ended power amplifier carefully sized to deliver around −7 dBm power to a 50- antenna with an integrated 13.9-nH RF-choke spiral inductor and 9-pF by-pass capacitors (MIM). This output stage consumes 2.2 mA current from a 1.5 V supply.

3. A 400 MHz LC Tank VCO Directly Loaded with a Poly-Phase Filter

In this section, the circuit design parameters and the measurement results of a poly-phase filter loaded 400 MHz LC tank VCO are discussed.

3.1. Circuit Design

As shown in Figure 3(b), a topology that uses nMOS-pMOS cross-coupled pairs with pMOS tail current source was chosen for the core VCO design. Using both nMOS and pMOS pair gives double amplification for a given current. In addition, this circuit can be optimized to have more symmetry in the output waveform leading to a further phase noise reduction [15]. Due to its lower flicker noise pMOS transistor was used as a tail current source.

For a given process and VCO topology, enlarging the oscillation amplitude is a very efficient way of reducing the phase noise [16]. For a given current level, this can be achieved by maximizing the values of the resonant tank inductors [17]. However, there are some serious limitations on the value of the inductor if the inductor is to be integrated in a CMOS process. As the value of the inductance in a spiral inductor increases, the resistive losses associated with it would degrade the Q of this inductor, which is the most important phase noise source in a fully integrated VCO. Thus, it is desirable to construct large inductors with very low resistive losses [16]. An 8-turn 22.4 nH spiral inductor with a trace width of m and gap of m is used for this design. Only the top metal layer (metal6) was used for the spirals which would result in a total series resistance of at 400 MHz. The quality factor of this inductor at 400 MHz is 5.2. The total tank capacitance corresponding to this inductance value is  pF. This total capacitance represents all the parasitic capacitances associated with the FETs, capacitive loading due to poly-phase filter, 3-bit binary weighted MIM-Caps for calibration, and varactor diodes for tuning. Moreover, two switchable 7-fF metal2-metal3 capacitors were used for FSK modulation.

The basic configuration for an LC tank oscillator is given in Figure 3(a) [16]. To satisfy the oscillation condition, the transconductance necessary to have the unity loop gain at the oscillation frequency, , can be calculated from the transfer function as [16] where RP is the parallel tank resistance, RL is the inductor series resistance, and RC is the varactor series resistance. The most important term in determining the value of is the series resistance of the inductor at 400 MHz, which is approximately 20  Using (1), the transconductance required to compensate the losses can be calculated as Therefore, each transistor should have a gm of 6.5 mS. Thus, with a safety factor of 3, the design assumes 20-mS transconductance for each device. Current required to achieve the given transconductance value with an over-drive voltage of would be Hence, the total tail current of VCO core is set to be 2 mA from a 1.5-V supply during the simulations. The corresponding transistor W/L ratios are for nMOS pair transistors and three times bigger for the pMOS pair devices.

Using a poly-phase filter to generate quadrature phases is a popular approach for low power, I-Q mismatch tolerant applications [18, 19]. In general, these filters have low input impedance and require power hungry buffers to drive them after the VCO. They might also require buffers following them to drive the mixers (Figure 1). These buffers isolate the mixer input capacitance from the filter and also provide the signal swing required for the mixer.

For this specific application, taking advantage of relatively low operating frequency, both buffers have been removed and the VCO is directly loaded with a single-stage poly-phase filter as shown in Figure 3(b) (only single stage is used to limit the filter loss). Rfil and Cfil were chosen very carefully to maximize the filter input impedance while keeping capacitance value large enough compared to total parasitic capacitance in order not to deteriorate the I-Q mismatch. The total input capacitance of mixer and power amplifier driver together with the parasitic capacitance of the poly-resistors to substrate is around 38 fF in this design. Thus, Cfil was chosen to be 132.7 Ff (four times bigger than total parasitic capacitance) which would lead to a resistor value of  k. The filter impedance for these values can be reflected to the VCO as parallel combination of and [19]. This 3 k resistor value is 6 times larger than the total effective parallel tank resistance (dominated by inductor series resistance Rind) . Thus, the loading due to the filter impedance is negligible. The capacitive part of the filter impedance is absorbed into the total tank capacitance to generate 400 MHz center frequency.

3.2. Measurement Results

The design has been fabricated in 0.18m TSMC CMOS process. The total die area including the bonding pads, a fully integrated power amplifier with the RF choke coil, and the by-pass capacitors is 1.2 mm 1.2 mm (Figure 4). LLP-40 leadless 40-pin RF package is used for the measurements. The oscillator can sustain the oscillation with a current as low as 800A. The detailed spectrum measurements were done with a core supply current of 1.25 mA, leaving some safety margin. The measured spectrum and the tuning characteristics are shown in Figure 5. The desired tuning characteristics were obtained with a total tuning range of 90 MHz spread into 3-bit controlled 8 clusters. The VCO gain inside every cluster is around 15 MHz/V as expected. Although the most significant bit (MSB) of the calibration input causes a larger step in the tuning range, a safe overlap can still be observed. The FSK control bits caused 60-kHz tones around the center frequency. Although this tone frequency still can be employed with FSK, this value can easily be tuned to the desired 70-kHz tone in the next iteration of the design by modifying the FSK capacitors. The phase noise measurement is done with Agilent E5052A. The phase noise at an offset of 160 kHz is −98 dBc/Hz, which is far below the prerequisite value for the application. The phase noise plot is shown in Figure 6(a). Figure 6(b) shows the phase noise values at the offsets of interest for various power levels.

4. An 800 MHz LC Tank VCO with a Master-Slave Divider

Another way to generate quadrature signals is to use a master-slave divide-by-2 circuit following a VCO operating at double frequency. In this section, the performance of an 800 MHz LC tank VCO with an analog master-slave divider is discussed. The divider outputs drive the same mixer and power amplifier load as in the case of first design (as shown in Figure 1).

4.1. Circuit Design

Since the fast analog D-flip-flops of the divider circuit needs to be driven with high swing inputs, a VCO topology with only nMOS cross-coupled pair is used to have a higher swing at the oscillator output. The circuit schematic of the design including the divider is shown in Figure 7. Two 13.69-nH spiral inductors with 7 turns are used for this 800-MHz LC tank. The top metal (metal6) with conductor width m and conductor spacing m yields an effective series resistance of 13 . Q factor for this inductor is around 4.2 at the frequency of 800 MHz. The total of 2.89 pF tank capacitance includes varactor diode capacitances, 3-bit binary weighted switchable MIM-caps, parasitic gate-source, and drain-source capacitances of the cross coupled nMOS pair and the parasitic input gate capacitance of the divider circuit. Two 5-fF metal2-meatl3 capacitances are used for direct FSK modulation by the base-band binary data. The total effective series resistance of the tank was estimated to be 16  with an additional up to 3- varactor series resistance. Again using (2), the overall required transconductance is calculated to be 3.36 mS. Assuming a safety factor of 3, each nMOS device of the cross-coupled pair should have a gm of around 20 mS to sustain reliable oscillation. This transconductance value can be obtained by having 1 mA current through each branch with 120 mV overdrive voltage across 100m width minimum channel length nMOS devices. A current source pMOS device of 400m channel width and 0.3m channel length can support this 2-mA total current with an overdrive voltage of 140 mV.

A very common topology shown in Figure 7 was used for fast divide-by-2 operation. In this design, M3 and M4 would not allow a large voltage drop at the drains of M1 and M2, which otherwise would push M11 into triode region in case of a large VCO output driving this stage, particularly in the case of a low supply voltage. Transistors were carefully sized to achieve successful division using a 1.5-V supply with minimum power consumption. The divider circuit can directly drive the mixers and the PA consuming 400A from a 1.5-V supply [20].

4.2. Measurement Results

The design has been fabricated in 0.18m TSMC CMOS process. The total die area including the bonding pads, a fully integrated power amplifier with the RF choke coil and the by-pass capacitors is 1.1 mm 1.2 mm (Figure 8). The VCO core and the divider circuit consume 2.2 mA from a 1.5-V supply. The measured tuning characteristic of the design is shown in Figure 9. The desired tuning characteristics were obtained with a total tuning range of 70 MHz spread into 3-bit controlled 8 clusters. The linear tuning region of this VCO is much less compared to linear tuning range of the 400 MHz design. However, due to large overlapping margins across the clusters, the comparator thresholds can be set accordingly to keep the VCO in the linear part of the tuning curve as shown in Figure 9. The VCO gain inside every cluster is around 17 MHz/V. The FSK control bits in this case caused 120-kHz tones around the center frequency. The measured spectrum and the phase noise plot are shown in Figure 10. The phase noise at an offset of 160 kHz is −97.7 dBc/Hz, a value which is very close to the −98 dBc/Hz value obtained from the previous design.

5. A Four-Stage Differential Ring VCO

Since the phase noise requirement of the application is relatively relaxed, the performance of a four-stage differential ring VCO is evaluated as a low power alternative to LC tank VCOs. There is no extra step to generate the quadrature outputs in the case of this four-stage ring VCO. The area of the design, most of which is occupied by the on-chip inductor of the PA, is considerably less compared to the LC tank VCOs (Figure 9). The same PA and mixer loads as in the case of LC tank designs are driven by the differential buffers following the Ring VCO.

5.1. Circuit Design

Ring oscillators are generally avoided in communication circuit applications due to their poor phase noise and linearity performance relative to LC tank oscillators. However, some researchers have investigated the ways to improve the phase noise and linearity of the ring VCOs [21, 22]. The noise transfer function can be calculated using a linear model for the oscillator. In the paper, these calculations were supported with the measurements in order to predict the thermal noise contributions of the delay elements accurately. A four-stage differential VCO was optimized to achieve the desired tuning and FSK modulation characteristics satisfying the phase noise requirement (−83 dBc/Hz at 160 kHz offset). The schematic of the design including an individual delay element is shown in Figure 11. Every delay cell in this VCO gets three bit calibration control and two bit FSK control signals. These two bit FSK data turn long channel devices M11 and M12 on and off, causing the total sink current change in slight amounts such that frequency deviations will be around 80 kHz. The delay cell topology proposed in [22] is modified to have additional calibration and FSK control. This topology is particularly suitable for the application due to two main reasons. First, one can obtain a very low VCO gain, Kvco, by properly sizing the devices M5 and M6 relative to the devices M3 and M4. Second, the tuning devices M5 and M6 would stay in saturation even for very small control voltage levels. Using Barkhausen oscillation criteria, oscillation frequency for an n-stage ring oscillator can be written down as [21, 22] where, R and C are the resistance and capacitance, respectively, at the output node of individual delay cells. For this design the output impedance is dominated by 1/gm3,4. Since the devices M3 and M4 are mostly in saturation, the relation between the control voltage and the oscillation frequency can be written down as Although not perfectly linear, monotonic, and linear-like characteristic can be maintained over the full useful tuning range due to low supply voltage.

The circuit was optimized in simulations to obtain −82 dBc/Hz phase noise at a 160 kHz offset. Spectre was used for phase noise optimization. The simulated current consumption of the VCO core including the differential buffers was 700A from a 1.5-V supply.

5.2. Measurement Results

The design was laid out on the upper left corner of the 800-MHz LC tank VCO die (Figure 8). The same inductively loaded two-stage PA follows the buffers isolating the delay cells. The measured spectrum and the tuning characteristic of the ring VCO are shown in Figure 12. Very fine distributed overlapping tuning clusters were obtained as predicted. The linearity of this ring VCO even outperforms the linearity of its LC tank counterparts. A very serious drawback of this ring VCO was the excessively high susceptibility of the oscillating frequency to the noise in the supply and control lines. Although an average frequency deviation of observed with FSK control, this drawback associated with this ring VCO should be addressed in order to be able to observe accurate 70 kHz FSK tones.

The phase noise at 160 kHz offset is −77 dBc/Hz, which is extracted by looking at the power from the measured spectrum at this offset and subtracting the resolution bandwidth. The measured current consumption was 738A from a 1.5-V supply.

6. Comparison and Conclusion

Three different fully integrated VCOs including the driving buffers and the power amplifiers were designed, and fabricated in 0.18m TSMC CMOS process to evaluate the best option for an MICS band transceiver operating at the new 402–405 MHz band. Although it consumes very low power and occupies very small die area, the poor frequency stability of ring VCO makes it difficult to obtain a reasonable FSK tone for 300 kHz channel spacing in MICS band. Moreover, the measured phase noise was 5 dB more than the predefined maximum level. The 800 MHz LC tank VCO with master-slave divider achieves almost the same phase noise performance at the expense of almost double power consumption, compared to the 400 MHz LC tank VCO directly loaded with poly-phase filter. The linearity of the tuning curve of 800 MHz design is worse than the 400 MHz one. The measurement results of these three architectures were summarized in a comparison table (Table 1). In conclusion, a carefully designed 400 MHz LC tank driving a poly-phase filter was proven to be the best option for this application.


VCO typeCurrent consumptionDie areaPhase noise @ 160 kHz offsetLinearityFrequency stabilitySupply noise sensitivity

Ring0.74 mA0.2 mm × 0.2 mm−77 dBc/HzGoodPoorSensitive
LC-tank divided2.20 mA0.4 mm × 0.7 mm−97 dBc/HzModerateGoodImmune
LC-tank with PF1.25 mA0.6 mm × 0.8 mm−98  dBc/HzModerateGoodImmune

Acknowledgments

The authors would like to thank Masood Yousefi, Ali Kiaei, Bijoy G Chatterjee, Ahmad Bahai, Raj Subramoniam, and Virginia Abellera of National Semiconductor for their support and collaboration in the project. M. Yuce’s work is supported by the Australian ARC discovery Grant no. DP0772929.

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Copyright © 2008 Ahmet Tekin et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


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