VLSI Design

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Research Article

A New XOR Structure Based on Resonant-Tunneling High Electron Mobility Transistor

Table 3

The comparison between proposed XORs.

Input voltages and marginsOutput margineNumber of components PerformanceDesign consideration

6-transistor XORHigh Logic: 5 VNot mentionedFET : 6Simulation results up to 50 MHz, Maximum delay:There are two types of implementation with different characteristics
Low Logic: 0 VFigure 3(a): 3.98 nanoseconds
Figure 3(b): 1.75 nanoseconds

4-transistor XORHigh Logic: 3.3 VNot mentionedFET : 4Simulation results up to 200 MHz, delay: 350 picosecondsNo power supply (powerless design)
Low Logic: 0 V

Quenching of series-connected NDR devicesHigh Logic: 0.5 VNot mentionedRTD : 3Not mentionedFor the XOR function, two FETs can be eliminated by exact design of each RTD area
Low Logic: 0 VFET : 6

RTHEMT XOR (This paper)High Logic: 1.1–1.4 VHigh logic: FET: 2Max Freq: 90.90 GHz1. One state has nearly zero static power dissipation.
Low Logic:  0–0.3 VLow Logic:    RTHEMT: 1Max Delay: 11 picoseconds2. In highest frequency it dissipates only

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