Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations

Table 2

Repeat and Weight Profiles of 2-b WBTC.

Repeats	Near GND						Near Vdd
16		T11
12	T0, T7
8		T4
6				T17, T22	T15,T20	T23	T21
4			T1, T8, T14, T19			T18,T26	T16, T25
2				T5, T12	T2,T9,T24	T13	T10
1						T6	T3, T27
Weight	0.5	0.4	0.3	0.2	0.15	0.1	0.05