VLSI Design

A Cost-Effective 10-Bit D/A Converter for Digital-Input MOEMS Micromirror Actuation

Selected Papers from the Midwest Symposium on Circuits and Systems

An Approach for Implementing State Machines with Online Testability

Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

CORDIC Architectures: A Survey

Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds?—A Survey

Nonlinear Circuit Analysis via Perturbation Methods and Hardware Prototyping

FPGA Implementation of an Amplitude-Modulated Continuous-Wave Ultrasonic Ranger Using Restructured Phase-Locking Scheme

Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs

Local Biasing and the Use of Nullator-Norator Pairs in Analog Circuits Designs

Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations

Implementation of Hardware-Accelerated Scalable Parallel Random Number Generators

A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs

Error Immune Logic for Low-Power Probabilistic Computing

Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments

VLSI Design

Table of Contents

Table of Contents: 2010

A Cost-Effective 10-Bit D/A Converter for Digital-Input MOEMS Micromirror Actuation

Selected Papers from the Midwest Symposium on Circuits and Systems

An Approach for Implementing State Machines with Online Testability

Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

CORDIC Architectures: A Survey

Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds?—A Survey

Nonlinear Circuit Analysis via Perturbation Methods and Hardware Prototyping

FPGA Implementation of an Amplitude-Modulated Continuous-Wave Ultrasonic Ranger Using Restructured Phase-Locking Scheme

Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs

Local Biasing and the Use of Nullator-Norator Pairs in Analog Circuits Designs

Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations

Implementation of Hardware-Accelerated Scalable Parallel Random Number Generators

A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs

Error Immune Logic for Low-Power Probabilistic Computing

Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments