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VLSI Design
Table of Contents
Special Issues
VLSI Design
/
2010
/
Article
/
Tab 2
/
Research Article
Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations
Table 2
Repeat and Weight Profiles of 2-b WBTC.
Repeats
Near GND
Near
Vdd
16
T
11
12
T
0
, T
7
8
T
4
6
T
17
, T
22
T
15
,T
20
T
23
T
21
4
T
1
, T
8
, T
14
, T
19
T
18
,T
26
T
16
, T
25
2
T
5
, T
12
T
2
,T
9
,T
24
T
13
T
10
1
T
6
T
3
, T
27
Weight
0.5
0.4
0.3
0.2
0.15
0.1
0.05