Research Article
Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations
Table 3
Characteristics of Benchmark Circuits.
| | Design | # Inputs | # Outputs | # Paths | # Transistors |
| | CCT-2 | 8 | 6 | 6 | 7 | | 2-b WBTC | 4 | 6 | 34 | 28 | | 4-b UWBTC | 4 | 15 | 83 | 83 | | 74181-CLA | 10 | 6 | 18 | 24 | | 74181-E Mod | 8 | 6 | 6 | 7 | | C2670-CLA | 24 | 1 | 15 | 39 | | C3540-CC5 | 7 | 1 | 4 | 7 | | C3540-CC8 | 7 | 3 | 17 | 35 | | C3540-CC9 | 8 | 3 | 22 | 47 | | C3540-UM12-7 | 9 | 1 | 24 | 50 | | C5315-CalP2 | 6 | 1 | 7 | 14 | | C5315-GLC4_2 | 8 | 1 | 5 | 8 | | C5315-CB4 | 9 | 1 | 5 | 9 | | C7552-GLC5_1 | 8 | 1 | 4 | 9 | | C7552-CGC34_4 | 9 | 4 | 14 | 9 | | C7552-CGC17 | 6 | 1 | 3 | 5 | | C7552-CGC20 | 7 | 1 | 4 | 7 |
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