Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations

Table 4

Optimization results from the LBMP Algorithm.

Design	Initial delay	Final delay	Delay reduction	Uncertainty reduction	Power increase	Area increase
	(psec)	(psec)	(%)	(%)	(%)	(%)
CCT-2	226	109	52	46.8	8.6	53.1
2-b WBTC	355	157	55	48.6	2.3	65.5
4-b UWBTC	152	103	33	63.6	14.0	12.6
74181-CLA	209	103	51	46.8	22.3	53.1
74181-E Mod	225	110	51	47.3	9.4	54.2
C2670-CLA	391	206	47	52.7	14.4	58.5
C3540-CC5	144	77	46	61.6	13.2	43.3
C3540-CC8	427	216	50	53.5	14.2	62.1
C3540-CC9	341	202	41	64.3	18.4	32.1
C3540-UM12-7	485	178	63	43.7	n/a	33.4
C5315-CalP2	230	137	39	40.0	2.7	9.2
C5315-GLC4_2	197	122	38	40.4	18.4	12.2
C5315-CB4	243	134	45	48.3	15.2	32.3
C7552-GLC5_1	196	95	52	34.3	17.5	62.8
C7552-CGC34_4	468	161	65	67.7	9.5	51.8
C7552-CGC17	136	84	39	35.0	14.2	21.3
C7552-CGC20	144	78	46	24.4	13.4	19.3
Average (%)			47.8	48.1	13.0	39.8