Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations

Table 5

Power Delay Product optimization results from the proposed algorithm.

Design	Initial PDP (fWs)	Final PDP (fWs)	PDP Reduction (%)
CCT-2	3.57	1.87	47.49
2-b WBTC	13.66	6.185	54.74
4-b UWBTC	6.61	5.11	22.57
74181-CLA	5.04	3.04	39.55
74181-E Mod	3.55	1.90	46.46
C2670-CLA	2.97	1.75	41.07
C3540-CC5	1.09	0.66	38.78
C5315-CalP2	7.47	4.57	38.78
C5315-GLC4_2	3.68	2.70	26.48
C5315-CB4	4.61	2.93	36.43
C7552-CGC34_4	16.42	6.19	62.26
C7552-CGC17	1.63	1.15	28.97
C7552-CGC20	1.09	0.67	38.70
Average (%)			40.17