Research Article
Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments
Table 2
Device Utilization Summary on Xilinx Virtex-II Pro FPGA (XC2VP30).
| Network size | Number of slice registers | Number of block RAMs | Number of MULT | Used | Utilization | Used | Utilization | Used | Utilization |
| | 2724 | 19% | 8 | 5% | 12 | 8% | | 4929 | 35% | 16 | 11% | 24 | 17% | | 7896 | 57% | 24 | 17% | 36 | 26% | | 10589 | 77% | 32 | 23% | 48 | 35% | | 12408 | 90% | 40 | 29% | 60 | 44% | | 3661 | 26% | 8 | 5% | 18 | 13% | | 7327 | 53% | 16 | 11% | 36 | 26% | | 11025 | 80% | 24 | 17% | 54 | 39% | | 14763 | 107% | 32 | 23% | 72 | 52% | | 18456 | 134% | 40 | 29% | 90 | 66% | | 4783 | 34% | 8 | 5% | 24 | 17% | | 9646 | 70% | 16 | 11% | 48 | 35% | | 14587 | 106% | 24 | 17% | 72 | 52% | | 19508 | 142% | 32 | 23% | 96 | 70% | | 24461 | 178% | 40 | 29% | 120 | 88% |
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