Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments

Table 2

Device Utilization Summary on Xilinx Virtex-II Pro FPGA (XC2VP30).

Network size	Number of slice registers		Number of block RAMs		Number of MULT$18\times 18\text{s}$
	Used	Utilization	Used	Utilization	Used	Utilization
$2\times 2$	2724	19%	8	5%	12	8%
$2\times 4$	4929	35%	16	11%	24	17%
$2\times 6$	7896	57%	24	17%	36	26%
$2\times 8$	10589	77%	32	23%	48	35%
$2\times 10$	12408	90%	40	29%	60	44%
$3\times 2$	3661	26%	8	5%	18	13%
$3\times 4$	7327	53%	16	11%	36	26%
$3\times 6$	11025	80%	24	17%	54	39%
$3\times 8$	14763	107%	32	23%	72	52%
$3\times 10$	18456	134%	40	29%	90	66%
$4\times 2$	4783	34%	8	5%	24	17%
$4\times 4$	9646	70%	16	11%	48	35%
$4\times 6$	14587	106%	24	17%	72	52%
$4\times 8$	19508	142%	32	23%	96	70%
$4\times 10$	24461	178%	40	29%	120	88%