Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments

Table 3

Device utilization summary on Xilinx Virtex-II pro FPGA (XC2VP70).

Network size	Number of slice registers		Number of block RAMs		Number of MULT$18\times 18\text{s}$
	Used	Utilization	Used	Utilization	Used	Utilization
$2\times 2$	2497	7%	8	2%	12	3%
$2\times 4$	4929	14%	16	4%	24	7%
$2\times 6$	7390	22%	24	7%	36	10%
$2\times 8$	9915	29%	32	9%	48	14%
$2\times 10$	12403	37%	40	12%	60	18%
$3\times 2$	3661	11%	8	2%	18	5%
$3\times 4$	7327	22%	16	4%	36	10%
$3\times 6$	11025	33%	24	7%	54	16%
$3\times 8$	14788	44%	32	39%	72	9%
$3\times 10$	18461	55%	40	12%	90	27%
$3\times 12$	22233	67%	48	14%	108	33%
$3\times 14$	25652	77%	56	17%	126	38%
$3\times 16$	29254	88%	64	19%	144	43%
$4\times 2$	4783	14%	8	2%	24	7%
$4\times 4$	9646	29%	16	4%	48	14%
$4\times 6$	14561	44%	24	7%	72	21%
$4\times 8$	19534	59%	32	9%	96	29%
$4\times 10$	24470	73%	40	12%	120	36%
$4\times 12$	29221	88%	48	14%	144	43%
$4\times 14$	34389	103%	56	17%	168	51%