VLSI Design

Research Article

Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

Figure 5

Full adder cells used for simulation.
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(a) C-CMOS
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(b) CPL
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(c) TFA
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(d) TGA
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(e) New 14T
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(f) 10T
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(g) New HPSC