Research Article
Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits
Table 4
Power, Delay, and Power-Delay Product (PDP) comparison of full adders using MDE and ADC algorithms.
| | 0.8 | 1.2 | 1.6 | 2.0 |
| Power (W) |
| C-CMOS | 1.52 | 2.36 | 4.60 | 8.24 | CPL | 1.42 | 3.65 | 5.21 | 9.27 | TFA | 1.07 | 3.44 | 5.29 | 10.27 | TGA | 1.1 | 3.49 | 5.31 | 10.4 | New 14T | 1.13 | 3.53 | 15.84 | 26.92 | 10T | 1.76 | 5.38 | 16.20 | 28.00 | New HPSC | 0.96 | 2.44 | 4.74 | 8.23 |
| Delay (ns) |
| C-CMOS | 0.29 | 0.26 | 0.30 | 0.29 | CPL | 0.37 | 0.34 | 0.28 | 0.30 | TFA | 0.34 | 0.29 | 0.24 | 0.21 | TGA | 0.36 | 0.31 | 0.29 | 0.25 | New 14T | 0.32 | 0.3 | 0.27 | 0.26 | 10T | 0.40 | 0.40 | 0.41 | 0.40 | New HPSC | 0.21 | 0.19 | 0.22 | 0.23 |
| Power-Delay product (fJ) |
| C-CMOS | 0.44 | 0.61 | 1.38 | 2.39 | CPL | 0.53 | 1.24 | 1.45 | 2.78 | TFA | 0.36 | 1.00 | 1.27 | 2.16 | TGA | 0.39 | 1.08 | 1.53 | 2.6 | New 14T | 0.36 | 1.05 | 4.2 | 6.9 | 10T | 0.70 | 2.15 | 6.64 | 11.20 | New HPSC | 0.20 | 0.46 | 1.04 | 1.89 |
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