Research Article
Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits
Table 5
Power, Delay, and Power-Delay Product (PDP) comparison of full adders using proposed transistor sizing algorithm (SEA).
| | 0.8 | 1.0 | 1.2 | 1.4 | 1.6 | 1.8 | 2.0 |
| Power (W) |
| C-CMOS | 0.94 | 1.54 | 2.36 | 3.46 | 4.87 | 6.63 | 8.42 | CPL | 1.41 | 2.30 | 3.57 | 5.27 | 7.35 | 9.89 | 12.93 | TFA | 0.95 | 1.66 | 2.62 | 3.63 | 5.17 | 7.15 | 9.23 | TGA | 1.07 | 1.73 | 2.72 | 3.95 | 5.48 | 7.40 | 9.60 | New 14T | 1.25 | 1.84 | 2.56 | 3.66 | 5.15 | 6.75 | 8.66 | 10T | 2.57 | 4.12 | 5.68 | 7.82 | 10.94 | 16.21 | 21.97 | New HPSC | 0.97 | 1.61 | 2.60 | 3.65 | 5.00 | 6.70 | 8.67 |
| Delay (ns) |
| C-CMOS | 0.38 | 0.22 | 0.17 | 0.13 | 0.11 | 0.10 | 0.10 | CPL | 0.27 | 0.17 | 0.13 | 0.11 | 0.09 | 0.08 | 0.08 | TFA | 0.26 | 0.13 | 0.09 | 0.08 | 0.07 | 0.06 | 0.05 | TGA | 0.24 | 0.15 | 0.11 | 0.09 | 0.07 | 0.06 | 0.06 | New 14T | 0.44 | 0.17 | 0.11 | 0.08 | 0.06 | 0.05 | 0.05 | 10T | 0.48 | 0.28 | 0.18 | 0.10 | 0.08 | 0.06 | 0.06 | New HPSC | 0.28 | 0.17 | 0.12 | 0.10 | 0.08 | 0.07 | 0.07 |
| Power-Delay product (fJ) |
| C-CMOS | 0.35 | 0.35 | 0.40 | 0.46 | 0.54 | 0.65 | 0.80 | CPL | 0.39 | 0.40 | 0.46 | 0.56 | 0.68 | 0.84 | 1.02 | TFA | 0.25 | 0.21 | 0.24 | 0.30 | 0.35 | 0.42 | 0.50 | TGA | 0.26 | 0.27 | 0.29 | 0.34 | 0.41 | 0.47 | 0.57 | New 14T | 0.55 | 0.32 | 0.28 | 0.29 | 0.32 | 0.36 | 0.43 | 10T | 1.24 | 1.14 | 1.01 | 0.80 | 0.84 | 0.98 | 1.24 | New HPSC | 0.27 | 0.27 | 0.31 | 0.36 | 0.42 | 0.50 | 0.60 |
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