Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

Table 6

Power, Delay, and Power-Delay Product (PDP) comparison of full adders using Chang’s algorithm.

$V_{\text{DD}}(\text{V})$	0.8	1.0	1.2	1.4	1.6	1.8	2.0
Power ($\mu$W)
C-CMOS	0.92	1.51	2.33	3.35	4.68	6.32	8.20
CPL	1.32	2.18	3.38	4.95	6.91	9.34	12.23
TFA	0.92	1.54	2.41	3.53	4.93	6.70	8.83
TGA	0.96	1.60	2.47	3.62	5.03	6.78	8.90
New 14T	0.89	1.48	2.26	3.31	4.62	6.30	8.33
10T	1.78	2.98	5.14	8.17	13.10	20.65	27.17
New HPSC	0.95	1.58	2.40	3.44	4.77	6.44	8.27
Delay (ns)
C-CMOS	0.39	0.25	0.18	0.14	0.12	0.11	0.10
CPL	0.36	0.24	0.19	0.16	0.14	0.13	0.12
TFA	0.40	0.28	0.21	0.18	0.16	0.14	0.13
TGA	0.41	0.25	0.18	0.15	0.13	0.11	0.11
New 14T	0.68	0.20	0.20	0.16	0.14	0.13	0.12
10T	4.41	1.51	0.39	0.17	0.10	0.11	0.08
New HPSC	0.29	0.17	0.12	0.12	0.09	0.08	0.09
Power-Delay product (fJ)
C-CMOS	0.36	0.38	0.43	0.49	0.59	0.74	0.89
CPL	0.48	0.54	0.66	0.82	1.02	1.27	1.57
TFA	0.40	0.44	0.52	0.64	0.79	0.98	1.21
TGA	0.40	0.41	0.46	0.55	0.66	0.81	0.99
New 14T	0.67	0.34	0.29	0.55	0.67	0.84	1.05
10T	7.80	4.50	2.05	1.39	1.96	2.47	2.30
New HPSC	0.27	0.28	0.30	0.43	0.47	0.54	0.80