Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

Table 7

Delay comparison (approximate) between MDE and ADC, Chang’s, and proposed transistor sizing algorithm (SEA) of full adders with a supply voltage of 1.2 V.

Full adder	Algorithm
	MDE & ADC	Chang’s algorithm	SEA
C-CMOS	0.26	0.18	0.17
Improvement	34.62%	5.56%
CPL	0.34	0.19	0.13
Improvement	61.76%	31.58%
TFA	0.29	0.21	0.09
Improvement	68.97%	57.14%
TGA	0.31	0.18	0.11
Improvement	64.52%	38.9%
New 14T	0.3	0.2	0.11
Improvement	63.33%	45%
10T	0.40	0.39	0.18
Improvement	55.00%	53.85%
New HPSC	0.19	0.12	0.12
Improvement	36.84%	0%
Average	55.01%	33.16%
Improvement