Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

Table 8

PDP comparison (approximate) between MDE and ADC, and proposed transistor sizing algorithm (SEA) of full adders with a supply voltage of 1.2 V.

Full adder		Algorithm
	MDE & ADC	SEA	Improvement
C-CMOS	0.61	0.40	34.43%
CPL	1.24	0.46	62.90%
TFA	1.00	0.24	76.00%
TGA	1.08	0.29	73.15%
New 14T	1.05	0.28	73.33%
10T	2.15	1.01	53.02%
New HPSC	0.46	0.31	32.61%
Average Improvement: 57.92%