Post-CTS Delay Insertion

Table 2

Post-CTS Delay insertion results for a suite of ISCAS'89 benchmark circuits.

Circuit info			Clock	Violation data			Insertion data
Circuit	$N$	$\#\mathit{\text{paths}}$	$T$	$\#p^{\text{vio}}$	$\text{\%}{p}^{\text{vio}}$	$\sum \text{vio}$	$\sum \mathrm{\Delta }$	$(\sum \mathrm{\Delta })/N$	Metric
s1196	18	20	20.8	1	5.0%	0.5	10.8	0.6	2.8%
s1423	74	1471	92.2	77	5.2%	1070.7	1531.8	20.7	22.5%
s1488	6	15	32.2	12	80.0%	80.8	61.2	10.2	31.7%
s6669	239	2138	128.6	68	3.2%	1630.2	6811.5	28.5	22.1%
s9234	228	247	75.8	86	34.8%	2204.3	N/A	N/A	N/A
s13207	669	3068	85.6	81	2.6%	1020.5	6279.2	9.4	11.0%
s15850	597	14257	116.0	406	2.8%	5025.4	11581.8	19.4	16.7%
s15850.1	534	10830	81.2	774	7.1%	8580.2	5767.2	10.8	13.3%
s35932	1728	4187	34.2	794	19.0%	6224.5	11232.0	6.5	19.0%
s38417	1636	28082	69.0	2206	7.9%	18811.2	12270.0	7.5	10.9%
s38584	1452	15545	94.2	178	1.1%	1837.1	34412.4	23.7	25.2%
Average					15.3%		8314.6	10.9	15.9%