Post-CTS Delay Insertion

Table 4

Clock period optimization with respect to the maximum possible improvement.

Circuit info	Clock period with total delay buffering 5% $T_{zs}$$N$				Clock period with total delay buffering 10% $T_{zs}$$N$
Circuit	[2]	Improvement	Proposed	Improvement	[2]	Improvement	Proposed	Improvement
s1196	17.36	34%	14.24	66%	16.32	45%	12.16	86%
s1423	87.59	31%	82.98	62%	82.98	62%	77.40	100%
s1488	30.59	50%	29.09	97%	29.09	97%	29.00	100%
s6669	122.17	34%	115.74	68%	115.74	68%	109.80	100%
s9234	299.41	7%	295.62	13%	295.62	13%	288.04	27%
s13207	81.32	15%	77.04	30%	77.04	30%	68.48	60%
s15850	110.20	18%	104.4	36%	104.40	36%	92.8	72%
s15850.1	77.14	17%	73.08	34%	73.08	34%	65.18	67%
s35932	33.99	2%	33.77	3%	33.77	3%	33.35	6%
s38417	65.55	13%	62.10	26%	62.10	26%	55.20	51%
s38584	89.49	16%	84.78	32%	84.78	32%	75.36	65%
Average		22%		43%		41%		67%