Post-CTS Delay Insertion

Table 5

Post-CTS limited delay insertion clock periods for a suite of ISCAS'89 benchmark circuits.

Circuit info	Clock period
Circuit	$k_1=0$	$k_1=0.1$	$k_1=0.2$	$k_1=0.3$	$k_1=0.4$	$k_1=0.5$	$k_1=0.6$	$k_1=0.7$	$k_1=0.8$	CSS ($k_1=\infty$)
s1196	20.80	14.24	12.16	10.80	10.80	10.80	10.80	10.80	10.80	10.80
s1423	92.20	82.98	77.40	77.40	77.40	77.40	77.40	77.40	77.40	77.40
s1488	32.20	29.09	29.00	29.00	29.00	29.00	29.00	29.00	29.00	29.00
s6669	128.60	115.74	109.80	109.80	109.80	109.80	109.80	109.80	109.80	109.80
s9234	303.20	295.62	288.04	280.46	272.88	265.30	257.72	250.14	246.00	246.00
s13207	85.60	77.04	68.48	60.16	57.10	57.10	57.10	57.10	57.10	57.10
s15850	116.00	104.40	92.80	83.60	83.60	83.60	83.60	83.60	83.60	83.60
s15850.1	81.20	73.08	65.18	61.12	57.40	57.40	57.40	57.40	57.40	57.40
s35932	34.20	33.77	33.35	32.92	32.49	32.06	31.64	31.21	30.78	20.4
s38417	69.00	62.10	55.20	48.30	42.20	42.20	42.20	42.20	42.20	42.20
s38584	94.20	84.78	75.36	66.77	65.20	65.20	65.20	65.20	65.20	65.20