Error Immune Logic for Low-Power Probabilistic Computing

Figure 10

The transistor level schematic of the carryout bit calculation using dual-rail asynchronous logic. Each bit is represented by a true and false line, $A_t$ and $A_f$, for example, where $A=1\to A_t=1,A_f=0$. If $A=0\to A_t=0,A_f=1$. The carryout bits are left as inverted because in dual-rail asynchronous adders, every other adder can calculate using inverted carry-in bits.