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VLSI Design
Volume 2010 (2010), Article ID 670476, 9 pages
Review Article

Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds?—A Survey

1Department of Electronics and Communication, Nirma University, Ahmedabad 382481, India
2Space Application Center, ISRO, Ahmedabad 380015, India

Received 23 July 2009; Revised 17 November 2009; Accepted 11 January 2010

Academic Editor: Avi Ziv

Copyright © 2010 Usha S. Mehta et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [3 citations]

The following is the list of published articles that have cited the current article.

  • Usha Mehta, K. S. Dasgupta, and N. M. Devashrayee, “Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method,” VLSI Design, vol. 2011, pp. 1–8, 2011. View at Publisher · View at Google Scholar
  • Ji-Shun Kuang, Ying-Bo Zhou, and Shuo Cai, “Adaptive EFDR coding method for test data compression,” Dianzi Yu Xinxi Xuebao/Journal of Electronics and Information Technology, vol. 37, no. 10, pp. 2529–2535, 2015. View at Publisher · View at Google Scholar
  • Shuo Cai, Yinbo Zhou, Peng Liu, Fei Yu, and Wei Wang, “A novel test data compression approach based on bit reversion,” IEICE Electronics Express, 2017. View at Publisher · View at Google Scholar