VLSI Design

VLSI Design / 2010 / Article / Tab 3

Research Article

A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs

Table 3

Data Widths and latencies of CalcDist.

Signal/CoreData WidthsLatency

Input32-bit (signed 12.20)
Subtractor32-bit i/p, 33-bit o/p1
Multiplier33-bit i/p, 66-bit o/p7
Adder165-bit i/p, 66-bit o/p1
Adder266-bit i/p, 67-bit o/p1
Output53-bit (unsigned 27.26)