A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs

Table 4

Data widths and latencies of CalcFunc module.

Signal/Core	Data Widths	Latency
		(clock cycles)
Inputs	Interpolation coefficients (a, b, c): signed 0.52,delta: signed 0.52	—
Multiplier1	52-bit i/p, 104 bit o/p	7
Adder1	52-bit i/p, 52-bit o/p	1
Multiplier2	52-bit i/p, 104-bit o/p	7
Adder2	52-bit i/p, 52-bit o/p	1
Output	Pairwise Potential Energy/Wave Function: signed 0.52	—