VLSI Design

VLSI Design / 2010 / Article / Tab 4

Research Article

A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs

Table 4

Data widths and latencies of CalcFunc module.

Signal/CoreData WidthsLatency
(clock cycles)

InputsInterpolation coefficients (a, b, c): signed 0.52,delta: signed 0.52

Multiplier152-bit i/p, 104 bit o/p7
Adder152-bit i/p, 52-bit o/p1
Multiplier252-bit i/p, 104-bit o/p7
Adder252-bit i/p, 52-bit o/p1

OutputPairwise Potential Energy/Wave Function: signed 0.52