A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops

Table 5

Comparis on between conventional ADPLL and proposed ADPLL

		Approaches
Items	Proposed ADPLL	Conventional ADPLL [11]	Conventional ADPLL [13]
Acquisition Time	10 cycles	18 cycles	50 cycles
Operation frequency range	570 MH$\text{z}~8$00 MHz	152 MH$\text{z}~3$66 MHz	50 MH$z~5$00 MHz
Lock-in range	Unlimited	Limited	Unlimited
Jitter	67 ps	150 ps	125 ps
Power consumption	19 mW @ 700 MHz	8.1–24 mW	40 mW @ 100 MHz