Table of Contents Author Guidelines Submit a Manuscript
VLSI Design
Volume 2011 (2011), Article ID 503025, 10 pages
http://dx.doi.org/10.1155/2011/503025
Review Article

Shedding Physical Synthesis Area Bloat

1IBM Austin Research Laboratory, Austin, TX 78758, USA
2IBM Waston Research Laboratory, Yorktown Heights, NY 10598, USA

Received 1 October 2010; Accepted 11 December 2010

Academic Editor: Shiyan Hu

Copyright © 2011 Ying Zhou et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. L. Trevillyan, D. Kung, R. Puri, L. N. Reddy, and M. A. Kazda, “An integrated environment for technology closure of deep-submicron IC designs,” IEEE Design and Test of Computers, vol. 21, no. 1, pp. 14–22, 2004. View at Publisher · View at Google Scholar · View at Scopus
  2. L. P. P. P. van Ginneken, “Buffer placement in distributed RC-tree networks for minimal Elmore delay,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '90), pp. 865–868, 1990.
  3. W. Shi and Z. Li, “A fast algorithm for optimal buffer insertion,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 6, pp. 879–891, 2005. View at Publisher · View at Google Scholar
  4. J. Lillis, C. K. Cheng, and T. T. Y. Lin, “Optimal wire sizing and buffer insertion for low power and a generalized delay model,” IEEE Journal of Solid-State Circuits, vol. 31, no. 3, pp. 437–446, 1996. View at Google Scholar
  5. Z. Li, C. N. Sze, C. J. Alpert, J. Hu, and W. Shi, “Making fast buffer insertion even faster via approximation techniques,” in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC '05), pp. 13–18, 2005.
  6. S. Hu, C. J. Alpert, J. Hu et al., “Fast algorithms for slew-constrained minimum cost buffering,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 11, pp. 2009–2022, 2007. View at Publisher · View at Google Scholar
  7. X. Tang, R. Tian, H. Xiang, and D. F. Wong, “A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints,” in Proceedings of the International Conference on Computer-Aided Design (ICCAD '01), pp. 49–56, 2001.
  8. P. Cocchini, “Concurrent flip-flop and repeater insertion for high performance integrated circuits,” in Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD '02), pp. 268–273, 2002.
  9. C. J. Alpert, A. Devgan, and S. T. Quay, “Buffer insertion with accurate gate and interconnect delay computation,” in Proceedings of the 36th Annual Design Automation Conference (DAC '99), pp. 479–484, 1999.
  10. C. J. Alpert, A. Devgan, and S. T. Quay, “Buffer insertion for noise and delay optimization,” in Proceedings of the 35th Design Automation Conference, pp. 362–367, 1998.
  11. Z. Li, C. J. Alpert, S. Hu, T. Muhmud, S. T. Quay, and P. G. Villarrubia, “Fast interconnect synthesis with layer assignment,” in Proceedings of the ACM International Symposium on Physical Design (ISPD '08), pp. 71–77, 2008. View at Publisher · View at Google Scholar
  12. C. Chu and D. F. Wong, “Closed form solution to simultaneous buffer insertion/sizing and wire sizing,” Proceedings of the ACM Transactions on Design Automation of Electronic Systems (TODAES '01), vol. 6, no. 3, pp. 343–371, 2001. View at Google Scholar
  13. C. P. Chen, C. C. N. Chu, and D. F. Wong, “Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD '98), pp. 617–624, 1998.
  14. S. Hu, M. Ketkar, and J. Hu, “Gate sizing for cell library-based designs,” in Proceedings of the 44th ACM/IEEE Design Automation Conference (DAC '07), pp. 847–852, June 2007. View at Publisher · View at Google Scholar
  15. Y. Liu and J. Hu, “A new algorithm for simultaneous gate sizing and threshold voltage assignment,” in Proceedings of the International Symposium on Physical Design (ISPD '09), pp. 27–34, 2009. View at Publisher · View at Google Scholar
  16. C. J. Alpert, S. K. Karandikar, Z. Li et al., “Techniques for fast physical synthesis,” Proceedings of the IEEE, vol. 95, no. 3, pp. 573–599, 2007. View at Publisher · View at Google Scholar
  17. S. K. Karandikar, C. J. Alpert, M. C. Yildiz, P. Villarrubia, S. Quay, and T. Mahmud, “Fast electrical correction using resizing and buffering,” in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC '07), pp. 553–558, 2007. View at Publisher · View at Google Scholar
  18. Z. Li, C. J. Alpert, S. Hu, T. Muhmud, S. T. Quay, and P. G. Villarrubia, “Fast interconnect synthesis with layer assignment,” in Proceedings of the ACM International Symposium on Physical Design (ISPD '08), pp. 71–77, April 2008. View at Publisher · View at Google Scholar