Table of Contents Author Guidelines Submit a Manuscript
VLSI Design
Volume 2011, Article ID 530851, 10 pages
http://dx.doi.org/10.1155/2011/530851
Research Article

Buffer Planning for IP Placement Using Sliced-LFF

1Tsinghua National Laboratory for Information Science & Technology, Tsinghua University, Beijing 100084, China
2Information, Production and Systems (IPS), Waseda University, Kitakyushu-shi 808-0135, Japan

Received 14 November 2010; Accepted 11 December 2010

Academic Editor: Shiyan Hu

Copyright © 2011 Ou He et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. J. A. Roy, S. N. Adya, D. A. Papa, and I. L. Markov, “Min-cut floorplacement,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 7, pp. 1313–1326, 2006. View at Publisher · View at Google Scholar · View at Scopus
  2. S. N. Adya and I. L. Markov, “Fixed-outline floorplanning: enabling hierarchical design,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 6, pp. 1120–1135, 2003. View at Publisher · View at Google Scholar · View at Scopus
  3. J. Cong, T. Kong, and D. Z. Pan, “Buffer block planning for interconnect-driven floorplanning,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD '99), pp. 358–363, November 1999.
  4. P. Sarkar, V. Sundararaman, and C. K. Koh, “Routability-driven repeater block planning for interconnect-centric floorplanning,” in Proceedings of the International Symposium on Physical Design (ISPD '00), pp. 186–191, April 2000.
  5. X. Tang and D. F. Wong, “Planning buffer locations by network flows,” in Proceedings of the International Symposium on Physical Design (ISPD '00), pp. 180–185, April 2000.
  6. F. F. Dragan, A. B. Kahng, I. Mandoiu, S. Muddu, and A. Zelikovsky, “Provably good global buffering using an available buffer block plan,” in Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD '00), pp. 104–109.
  7. C. W. Sham and E. F. Y. Young, “Routability driven floorplanner with buffer block planning,” in Proceedings of the International Symposium on Physical Design (ISPD '02), pp. 50–55, April 2002.
  8. F. Rafiq, M. Chrzanowska-Jeske, H. H. Yang, and N. Sherwani, “Inegrated floorplanning with buffer/channel insertion for bus-based microprocessor designs,” in Proceedings of the International Symposium on Physical Design (ISPD '02), pp. 56–61, April 2002.
  9. C. J. Alpert, J. Hu, S. S. Sapatnekar, and P. G. Villarrubia, “A practical methodology for early buffer and wire resource allocation,” in Proceedings of the 38th Design Automation Conference (DAC '01), pp. 189–194, June 2001.
  10. S. Chen, X. Hong, S. Dong, and Y. Ma, “A buffer planning algorithm based on dead space redistribution,” in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC '03), pp. 435–438, Kitakyushu, Japan, January 2003.
  11. I. H.-R. Jiang, Y.-W. Chang, J.-Y. Jou, and K.-Y. Chao, “Simultaneous floorplanning and buffer block planning,” in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC '03), pp. 431–434, Kitakyushu, Japan, January 2003.
  12. Y. Ma, X. Hong, S. Donag, S. Chen, C. K. Cheng, and J. Gu, “Buffer planning as ah integral part of floorplanning with consideration of routing congestion,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 4, pp. 609–620, 2005. View at Publisher · View at Google Scholar · View at Scopus
  13. Q. Dong, B. Yang, J. Li, and S. Nakatake, “Incremental buffer insertion and module resizing algorithm using geometric programming,” in Proceedings of the 19th ACM Great Lakes Symposium on VLSI (GLSVLSI '09), pp. 413–416, May 2009. View at Publisher · View at Google Scholar
  14. X. He, S. Dong, Y. Ma, and X. Hong, “Simultaneous buffer and interlayer via planning for 3D floorplanning,” in Proceedings of the 10th International Symposium on Quality Electronic Design (ISQED '09), pp. 740–745, March 2009. View at Publisher · View at Google Scholar
  15. S. Dong, X. Hong, Y. Wu, Y. Lin, and J. Gu, “VLSI block placement using less flexibility first principles,” in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC '01), pp. 601–604, Yokohama, Japan, January 2001.
  16. C. Alpert and A. Devgan, “Wire segmenting for improved buffer insertion,” in Proceedings of the 34th Design Automation Conference, pp. 588–593, June 1997.