Research Article
Vertical Gate RF SOI LIGBT for SPICs with Significantly Improved Latch-Up Immunity
Table 1
All parameters and symbols in Figure
8.
| | Power supply | | Resistance of drift region for electron current |
| | Load impedance | | Resistance of n-buffer region |
| | Bias voltage between gate and source electrodes | | Resistance of pinched P-well region |
| | Ground | | Resistance of drift region for hole current |
| | VG MOSFET | | Lateral transistor |
| | Vertical transistor | | Output |
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