Research Article | Open Access
Haipeng Zhang, Ruisheng Qi, Liang Zhang, Buchun Su, Dejun Wang, "Vertical Gate RF SOI LIGBT for SPICs with Significantly Improved Latch-Up Immunity", VLSI Design, vol. 2011, Article ID 548546, 9 pages, 2011. https://doi.org/10.1155/2011/548546
Vertical Gate RF SOI LIGBT for SPICs with Significantly Improved Latch-Up Immunity
Based on the previous achievements in improving latch-up immunity of SOI LIGBT, process simulation on our proposed VG RF SOI NLIGBT was carried out with TCAD to provide a virtually fabricated device structure. Then, an approximate latching current model was derived according to the condition of minimum regenerative feedback couple between the parasitic dual-transistors. The model indicates that its latching current is a few orders higher than those before. Further verification through device simulation was done with TCAD, which proved that its weak snapback voltage in the off state is about 0.5–2.75 times higher than those breakdown voltages reported before, its breakdown voltage in the off state is about 19 V higher than its weak snapback voltage, and its latching current density in the on state is about 2-3 orders of magnitude higher than those reported before at room temperature due to hole current bypass through P+ contact in P-well region. Therefore, it is characterized by significantly improved latch-up immunity.
Silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) has been widely used in smart power integrated circuits (SPICs) because of its high input impedance, low on-resistance, low forward voltage drop, high breakdown voltage, and compatibility with CMOS technologies [1–20]. SOI technology has been exhibiting more and more importance in the field of high-voltage integrated circuits (HVICs) and SPICs. Compared with bulk junction-isolated devices, SOI LIGBTs offer full dielectric isolation, reduced leakage currents, low-on state resistance, high input impedance, high packing density, fast switching speed, high noise immunity, and feasible operation at very high temperature. Therefore, SOI LIGBTs have attracted much attention in a wide variety of applications such as automotive electronics, consumer electronics, telecommunications, and industrial electronics [10–12, 14–20].
However, an inherent thyristor is involved in an SOI NLIGBT cell. The parasitic thyristor is composed of P anode, N-drift region, P-well, and N+/P+-cathode as shown in Figure 1. In a conventional SOI NLIGBT, hole current injected from P anode into drift region is collected by P-well and has to be transported through a pinched resistance along horizontal direction before it reaches P+ cathode, which results in a forward voltage drop across the P-well/N+ source junction. When the voltage drop grows sufficient to turn the vertical NPN transistor on at any point, the minimum regenerative feedback couple condition of the parasitic dual-transistors is satisfied and the parasitic thyristor latches up in a very short time. Gate control cannot be recovered until anode current falls below its holding current and it is very harmful to the device itself and the corresponding SPICs and HVICs [1–16].
Since 1990s, a lot of studies on improving latch-up immunity of SOI LIGBTs have been done extensively [11, 14–18]. Disney and Plummer presented a P+ sinker SOI LIGBT structure combined with a dual implanted P-well as shown in Figure 2, which yields a latch-up current density of 1355 A/cm2 with a 30 V gate-source drive voltage at the cost of adding some complexity to the fabrication process . Sumida et al. proposed a middle emitter SOI LIGBT structure as illustrated in Figure 3, which showed about 3.5 times and 5.5 times improvement of dynamic latch-up current density at R.T. and at 125°C, respectively, with an increment about 0.8 V of on-state voltage drop .
Park et al. proposed a buried gate SOI LIGBT shown in Figure 4, the latch-up current density of which is 4140 A/cm2 on condition that the thickness of SOI film, the doping concentration, channel length, threshold voltage, and drift region length are 1 μm, 1016 cm−3, 1.5 μm, 2.0 V, and 15 μm, respectively, at the cost of much complexity and less agility of partial SOI processes . Liang et al. put forward that a metal sinker could be used to replace the P+ sinker shown in Figure 2 and further penetrate the buried oxide layer, which improves heat transfer and diverts holes current to substrate so that the latch-up effect could be suppressed to some extent . Choi et al. proposed a dual-channel SOI LIGBT, which seems like a combination of the middle emitter structure and the conventional structure as illustrated in Figure 5 and a four times improvement of latch-up current density is obtained . In , a new small sized lateral trench electrode insulated gate bipolar transistor (LTEIGBT) was proposed. Its latch-up current density was 1230 A/cm2, which appears about a 10 times high as that of LIGBT and a 2.3 times high as that of LTIGBT.
2. Our Researches on Vertical Gate SOI LDMOS/LIGBT
In  we proposed a vertical gate (VG) SOI LDMOS structure named TGFPTD SOI LDMOS as shown in Figure 6, which consists of an N+ source, a vertical gate and plate, a P-well tied to the N+ source via a heavily doped P+ contact, a lateral N-drift region, an N-buffer region, and a step-type trench drain. Thus, it is featured of low on-state voltage drop, low on-state static resistor, and high off-state breakdown voltage. Moreover, it was proved feasible to fabricate in advanced SOI CMOS technologies by 2D TCAD simulation and its channel length could be controlled down to about 130 nm .
In order to improve latch-up immunity of SOI LIGBT further, we proposed a vertical gate (VG) RF SOI LIGBT structure based on all the achievements above as illustrated in Figure 7. The proposed VG RF SOI LIGBT was also proved feasible to fabricate in advanced SOI CMOS technologies and its channel length could be controlled down to about 170 nm by process simulation with Silvaco TCAD . From Figure 7 it could be obviously predicted that the hole current component flows through the P+ collector region completely, which could effectively eliminate the regenerative feedback couple between the parasitic dual-transistors and increase latch-up current density of VG RF SOI LIGBT by alleviating the impact of the parasitic lateral resister under the N+ source region in P-well. Moreover, the N-buffer region and the N+-shorted anode can further reduce the current gain of the lateral PNP transistor and restrict hole injection through its emitting PN junction, which might improve the latch-up current density further .
3. Device Structure and Basic Principle of VG SOI LIGBT
The proposed device structure of VG radio frequency (RF) SOI NLIGBT is illustrated in Figure 7. As can be seen in Figure 7 the proposed device cell consists of an SOI substrate, a top layer of silicon film on the SOI substrate, a thick field oxide layer on the silicon film, a vertical gate short channel NMOSFET with a deep trench gate and gate plate on one side of the silicon film, a low doped N-drift region in the middle of the silicon film, a heavier doped N-buffer region adjacent to the N-drift region, a P-P+ anode and a shallow N+ shorted anode with a drain metal electrode, and plate contacted on the other side.
The basic operation principle of the VG RF SOI LIGBT is very similar to that of an assembly of a VG MOSFET and a PNP BJT with a wide base region as the substrate is grounded. Take VG RF SOI NLIGBT for example, it lies in the off state when the gate-source bias voltage is less than the threshold voltage of its built-in VG nMOSFET and the drain-source bias voltage , where represents the breakdown voltage. It can be turned on as and . At the same time, plenty of electrons injected from source electrode flow through the channel of the NMOSFET and swarm into the accumulative region beside the trench gate plate isolated by the vertical gate oxide. Then they spread out in n-drift region along both vertical and horizontal dimensions and drift toward drain electrode as can be seen in Figure 7 indicated by . While the voltage drop across the PN-buffer junction approaches its turn-on voltage due to flowing through N-buffer region and N+ shorted anode, a lot of holes are injected from P anode into N-buffer region and drifting toward P+ source as well as recombining with electrons in N-buffer region and N-drift region simultaneously as can be seen in Figure 7 indicated by and , respectively. Injection of vast ambipolar carriers plasma into N-drift region and N-buffer region leads to a significantly reduced specific on-resistance due to conductance modulation effect so that a desired on-state drain current as well as an enough low on-state voltage drop could be obtained for the proposed VG RF SOI NLIGBT. Whether the proposed VG RF SOI NLIGBT is in the on state or breakdown state, its hole current component could mainly be bypassed through the P+ contact region in P-well which could alleviate and even eliminate the regenerative feedback couple between the parasitic dual-transistors so that its latch-up immunity could be significantly improved further.
4. Modeling for Latch-Up Effect of VG SOI LIGBT
As can be seen in Figure 7 a parasitic thyristor structure exists in the VG SOI NLIGBT cell, which consists of N+ source/P-well/(N-drift and N-buffer regions)/P-P+ anode. The dual-bipolar-transistor equivalent circuit of the parasitic thyristor is illustrated in Figure 8. All parameters and symbols in Figure 8 are outlined in Table 1.
Based on the proposed device structure, a good approximation of latch-up current can be derived by solving the current required to establish a voltage drop across the pinched vertical P-well/P+ contact region which is sufficient to forward-bias the P-well/N+ source junction. This approximation may be expressed as where is the minimum turn-on voltage of emitter junction of the parasitic vertical NPN transistor by considering the distribution of impurities in these regions, which may be expressed as where is the Boltzmann constant, is the thermodynamics temperature, is the absolute value of electron charge quantity, is the minimum pure impurity concentration in N+ source region, is the minimum pure impurity concentration in pinched P-well/P+ contact region, and is the intrinsic carrier concentration of silicon and may be approximately expressed as where is the rate between product of effective carriers’ mass and square of static mass of free electron and may be approximately expressed as 
represents energy gap of silicon which is a function of thermodynamics temperature , represents the parasitic resistance of pinched vertical P-well/P+ contact region per unit width. By considering the cross-section structure and the distribution of boron atoms in the pinched vertical P-well/P+ contact region, a dual trapezoid cross-section and vertical local linear approximation of boron distribution was adopted since the thickness of N+ source is only about 0.2 μm. Thus, may be derived out as where is hole mobility in bulk silicon. It was deduced by element integral method with independent 2D coordinates for each trapezoid approximation illustrated in Figure 9. is saturated channel current of the built-in nMOSFET in the VG RF SOI LIGBT cell which may be approximately expressed as where is surface electron mobility, is capacitance density of gate capacitor, is channel width of the built-in nMOSFET, and is effective channel length.
The latch-up currents at room temperature and 600 K could be obtained, respectively, by substituting (2), (3), (5), and (6) into (1) and simplifying where and are the minimum turn-on voltages of emitter junction of the parasitic vertical transistor at room temperature and at 600 K, respectively, and are the parasitic resistances of pinched vertical P-well/P+ source region per unit width at room temperature and at 600 K respectively, and are hole mobility in degenerated silicon at room temperature and at 600 K, respectively.
5. Analysis of Latch-Up Immunity
The P-type impurity concentration of low doped P-well region is about 1017–1018 cm−3 whether in conventional SOI LIGBT or in the proposed new SOI LIGBT structures mentioned above. However, the P-type impurity concentration of P+ contact region is about 1020–1021 cm−3 nearly in all SOI LIGBT structures. Therefore, the parasitic resistivity of pinched vertical P-well/P+ contact region is about 103 Ω·cm orders less than that of pinched lateral P-well region. Thus, in order to trigger the regenerative feedback of the parasitic thyristor in the proposed device, a much higher hole current is required flowing through the pinched P+ contact region to establish a high enough voltage drop across it than in the device structures mentioned in Figures 3–5 and 7. Consequently, the proposed device structure is featured of much higher latch-up immunity.
Besides, one of the main differences among our proposed device structure and those in Figures 3–5 is that a shallow trench N+ shorted anode is inserted in the drain region, through which a part of electron current component can be extracted directly to the drain electrode whether in the on state or during turn-off course that may significantly alleviate the over injection of hole across the P+-N-drift or P+-N-buffer junction and reduce the turn-off current tail. These might be improved further by inserting a P anode region between n-buffer region and P+ anode region as illustrated in Figure 7. As a result, the parasitic thyristor may be triggered very difficultly due to almost completely decoupling between the parasitic dual-transistors in our proposed VG RF SOI LIGBT device structure.
Consequently, the values of latch-up currents at room temperature and 600 K could be calculated at about 39.20 MA/cm2 and 15.49 MA/cm2, respectively, by substituting the device parameters given in Figure 7 into (7), which is a few orders of magnitude higher than those reported in [11, 14–18]. That is to say, the device structure proposed in Figure 7 is characterized by very high latch-up immunity in theory.
6. Simulation Results and Discussion
The simulated cross-section view of VG RF SOI NLIGBT with TCAD ATHENA in advanced SOI CMOS VLSI technologies is illustrated in Figure 7, which demonstrates that the proposed device structure is feasible to fabricate with advanced SOI CMOS VLSI technologies. Our simulated current-voltage characteristic with V at room temperature is illustrated in Figure 10. As can be seen in Figure 10 the proposed VG RF SOI NLIGBT appears as a weak snap back phenomenon at about 75 V drain-source voltage due to BJT behavior, which is much higher in magnitude than the breakdown voltage of conventional SOI LIGBT at about 20 V and those of other improved versions at about 40–50 V with similar drift region length and other related structure parameters [11, 14–18, 24–26]. The proposed VG RF SOI NLIGBT was not broken down until drain-source voltage is beyond 94 V, which is even 19 V higher in magnitude than its snapback voltage. This might be explained by the idea that the parasitic thyristor is prevented from being triggered and broken down prematurely mainly due to bypassing of hole current directly through P+ contact region in P-well.
(a) Simulated current-voltage characteristic at 𝑉 g s = 0 . 4 V
(b) Amplified current-voltage characteristic in green rectangle region
Furthermore, the simulated latch-up current at room temperature could be reversely derived out at about 106.1 kA/cm2 in linear approximation conservatively, which is still much higher in magnitude than those reported in references [11, 14–18].
Figure 11 illustrates the 2D distribution of current flow lines along the cross section of the proposed device structure in the breakdown state at room temperature. Figure 12 illustrates the 2D distribution of hole current component along the cross-section of the proposed device structure in the breakdown state at room temperature. Figure 13 illustrates the 2D distribution of electron current component along the cross-section of the proposed device structure in the breakdown state at room temperature.
There may be a few arguments deduced from Figure 11 to Figure 13. The first one is that the hole current of the proposed VG RF SOI NLIGBT is fully bypassed through P+ well contact region even in the breakdown state at room temperature. The second one is that the impact ionization mainly happens in the depleted region adjacent to drain region. The third one is that there may be a inversion layer generated on the interface between silicon film and buried oxide at a certain bias condition which conducts a considerable hole current component so that a vertical hole current component and a fly-back lateral current component flow through P-well toward P+ contact region in the off state that was neglected in modeling for latch-up effect of VG RF SOI LIGBT mentioned above. The fourth one is that very little hole current is injected from P anode which manifests that the breakdown current mainly consists of impact ionization current components and reverse drifting current components. Consequently, the generative feedback between the parasitic vertical NPN transistor and lateral PNP transistor is not turned on even in the breakdown state at room temperature.
Figure 14 illustrates the 2D distribution of electron current component along the cross-section of the proposed device structure in the on state at room temperature. Figure 15 illustrates the 2D distribution of hole current component along the cross-section of the proposed device structure in the on state at room temperature. As can be seen in Figure 14 the trace of electron current component along the cross-section of the proposed VG RF SOI NLIGBT appears as a horizontal “S” shape in the on state at room temperature which originates from N+ source electrode, flows through vertical N-type channel, congregates along vertical accumulation layer, expends into and travels through lateral N-drift region and N-buffer region in turn, bypasses the corner of P anode, penetrates the N+ shorted anode, and swarms into drain electrode. This might be mainly ascribed to a few phenomena as follows.(i)Electrons are injected through the vertical channel controlled by the vertical gate and accumulate beside the vertical gate plate isolated by vertical gate oxide.(ii)A depletion layer exists in the N-drift region beside the P-well/N-drift junction due to pseudo-JFET effect.(iii)Charge attraction force works since an electric field is built in drift region between heavily injected holes from P anode into N-buffer and N-drift region which is shown in Figure 15 and heavily injected electrons through vertical channel into N-drift and N-buffer region.(iv)Static Coulomb force works since substrate is grounded.(v)Impedance exists across the potential barrier of P/N-buffer junction.(vi)Electrons are extracted through N+ shorted anode.
As can be seen from Figure 15 a considerable vertical hole current component exists through the part of N-drift region under P-well and an obvious fly-back lateral current component exists also in the on state, which flows through P-well toward P+ contact region. Total on-state current density is about 4660 A/cm2 and above at V.
However, even in the on state there is not any minor current observed in P-well which indicates that the parasitic vertical NPN transistor is still in the off state. In other words, the parasitic thyristor is still untriggered due to the full decouple between the parasitic dual-transistors.
Figure 16 illustrates simulated 2D distribution of latch-up current density of the proposed device structure in near critical latch-up state. As can be seen from Figure 16 the latch-up current density is about in the order of 1 MA/cm2 and above, which is approximately an order of magnitude higher than that reversely derived out according to Figure 10 and about an order lower of magnitude than that calculated from the latch-up model established above.
Based on the latch-up model, an injected electron current from N+ source into P-well at a certain point on the interface of the N+ source/P-well junction should exist as the proposed device lies in latch-up state. This is indicated by Figure 17 which shows that a very low electron current flows through P-well region at its fingertip in near critical latch-up state. The very low electron current indicates that the parasitic vertical NPN transistor is driven into the on state and the regenerative feedback couple between the parasitic dual-transistor is wakened up simultaneously.
Based on the researches and analyses above, it could be concluded that the latch-up current of our proposed VG RF SOI NLIGBT at room temperature might be about two orders higher in magnitude than those of previously proposed device structures since the hole current component is mostly bypassed by P+ well contact region; the proposed VG RF SOI NLIGBT might be characterized by very high latch-up immunity whether it is in the off state or the on state and its breakdown voltage in the off state is about 2.0–4.7 times higher in magnitude than those before. Therefore, our proposed VG RF SOI NLIGBT will be more suitable for SPICs-related applications.
Furthermore, the device structure and process parameters of VG RF SOI NLIGBT may be optimized further to improve its latch-up immunity and our latch-up current model of the proposed VG RF SOI NLIGBT is a little crude due to some idealized assumptions and might be modified further according to simulation results and/or silicon verification in the future.
Moreover, it is suggested that the parasitic latch-up effect of SOI LIGBT be utilized to improve some of its main electric performances by combining with the BPL SOI substrate [27, 28], the integrated anti-ESD structure [29, 30], and the structure of thyristor so as to break through the ceilings of both on-state current and forward block voltage based on the proposed VG RF SOI NLIGBT structure.
The authors appreciate the authorization of using TCAD tools by Silvaco China. One of the authors appreciates the publication of his paper “Vertical Gate RF SOI LIGBT Without Latch-Up Susceptibility” by ISDRS 2009 without any payment although he could not attend the symposium since his visa was not authorized in time. Projects supported by the National Natural Science Foundation of China (Grant no. 60306003) and by the Science and Technology development plan of Zhejiang Province (Grant no. 2009C21G2040066).
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